Intellectual Property Cores
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Floating point unit set for space ASIC
A licence agreement has been signed for the use of the Gaisler Research Floating Point Unit (GRFPU) in the Cole ASIC developed by Saab Ericsson Space.
News from Gaisler Research, Jun 24, 2005
Serial RapidIO IP is proven in silicon
Jennic has successfully demonstrated its Serial RapidIO IP operating in conjunction with solutions from other RapidIO vendors.
News from Jennic, Jun 21, 2005
Prototype aids ASI systems development
IDT has developed an FPGA-based prototype technology that demonstrates the interworking of the common switch interface (CSIX) datapath protocol into ASI.
News from IDT, Jun 17, 2005
MPEG-4 based codecs pass handset tests
Winbond Electronics has successfully completed testing on its latest MPEG-4 based codec chips featuring intellectual property from IndigoVision.
News from IndigoVision, Jun 17, 2005
Cores take control of Flash memory security
Discretix and ARM have collaborated to offer an integrated secure Flash controller solution optimised for the rapidly growing removable and embedded Flash-based memory markets.
News from ARM, Jun 17, 2005
Licensee list tops the ton
ARC International has now licensed more than 100 companies to use its patented configurable SoC technology.
News from ARC International, Jun 17, 2005
Speedy serial PHYs run on 90nm processes
ARM has released its silicon-verified ARM Artisan Velocity Serial Link 200 PHY (physical layer) Series on leading 90nm process technologies, with immediate effect.
News from ARM, Jun 17, 2005
Macros speed SoC static RAM integration
1T-SRAM Classic Memory Macros are a family of preconfigured high-density high-speed low-power memory macros using silicon-proven 0.13-micron cores.
News from MoSys, Jun 16, 2005
IBM to use IP library for 65nm ASICs
ARM Artisan Metro low-power standard cell libraries, memory compilers and I/Os have been selected for IBM's newest 65nm application-specific integrated circuit product offering.
News from ARM, Jun 15, 2005
IP core manages ARC multiprocessing
A new electronic system level model demonstrates the seamless integration of multiple ARC family 600 cores, using Ignios SystemWeaver multicore-enabling technology.
News from Ignios, Jun 15, 2005
Compact cores create flexible resampling filters
A new range of fractional resampling architectures for FPGAs can be used to perform up-sampling or down-sampling of high-speed digital signals.
News from RF Engines, Jun 13, 2005
Graphics engine appears in new Freescale chip
Freescale Semiconductor's new i.MX31 mobile entertainment multimedia processor includes Imagination's PowerVR MBX IP.
News from Imagination Technologies, Jun 13, 2005
Reference platform shows off multicore DSP
A new reference platform demonstrates multiple CEVA-Teak DSP cores seamlessly operating together using Ignios' multicore-enabling SystemWeaver technology.
News from Ignios, Jun 13, 2005
Configurable core is chosen for broadband duties
IPWireless has taken a licence for the configurable ARC 725D processor core for use in its latest SoC targeted for next generation 3G TD-CDMA broadband wireless devices.
News from ARC International, Jun 13, 2005
IP platform extends down to 65nm process
ARM has worked with IBM and Chartered Semiconductor Manufacturing to make its Artisan Metro low-power platform available for the IBM-Chartered 65nm low-power common process platform.
News from ARM, Jun 7, 2005
DTV receiver SoC showcases IP cores
Silicon Hive has demonstrated a DTV receiver incorporating the world's first fully programmable system-on-chip (SoC) for digital TV demodulation.
News from Silicon Hive, Jun 7, 2005
FPGA PCI core comes with claims of versatility
CorePCIF is the newest member of Actel's popular PCI product family that also includes CorePCI and CorePCIX.
News from Actel Europe, Jun 6, 2005
Libraries set for shrink to 65nm
TSMC has enlisted Virage Logic Corp to develop libraries to support early users of its 65nm Nexsys process technology.
News from Virage Logic, Jun 2, 2005
IP cores are ready to run on latest FPGA family
Lattice Semiconductor has released a range of key ispLeverCore intellectual property (IP) modules for its recently announced LatticeXP FPGAs.
News from Lattice Semiconductor UK, Jun 1, 2005
Peking University picks PCI Express IP
A Mentor Graphics IP core based on the PCI Express architecture has been selected by the Microprocessor Development and Research Centre (MPRC) at Peking University.
News from Mentor Graphics UK, May 31, 2005
PCI Express IP core runs on Xilinx FPGAs
Mentor Graphics is the first third-party intellectual property (IP) vendor to achieve PCI Express specification compliance on the NitAl PExBuilder-X254 Platform.
News from Mentor Graphics UK, May 31, 2005
Stretch signs for gigabit MAC IP
Mentor Graphics has licensed its 10/100/1000Mbit/s Ethernet MAC intellectual property to Stretch, a pioneer and leader in software-configurable processor devices.
News from Mentor Graphics UK, May 31, 2005
IBM-Chartered supports IP with 90nm platform
IBM and Chartered Semiconductor Manufacturing are offering the ARM Artisan Metro low-power platform and the ARM Artisan Velocity high-speed PHY series for their 90nm common process platform.
News from ARM, May 30, 2005
FFT core makes the most of new FPGAs
A new IEEE754 compliant floating point fast Fourier transform core is designed for use with the latest generations of high performance programmable devices from vendors like Xilinx and Altera.
News from 4DSP, May 30, 2005
Talwalkar takes reins from Corrigan
The LSI Logic Board of Directors has unanimously appointed Abhi Y Talwalkar as the company's President and Chief Executive Officer.
News from LSI Logic Europe, May 30, 2005
Showing 776-800 of 1567 articles
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Featured articles
- LSI adds processor core and memory blocks to range
LSI has announced the addition of the multicore-capable PowerPC 476 microprocessor core and high-speed, embedded DRAM memory blocks to its portfolio of custom silicon intellectual property (IP).
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