Synopsys expands USB 2.0 PHY IP product range
A Synopsys product story
Edited by the Electronicstalk editorial team Nov 3, 2009
Synopsys has added the Designware USB 2.0 PicoPHY IP to its USB 2.0 PHY IP range, which has been deployed in 300 customer designs and in 50 process technologies ranging from 180nm to 32nm.
Targeted at mobile and high-volume consumer applications such as smartphones, mobile internet devices and netbooks, Designware USB 2.0 PicoPHY supports advanced 28nm processes in a 1.8V architecture, is 30 per cent smaller than the previous USB 2.0 PHY generation and offers a reduced pin count and low standby power consumption.
The Designware USB 2.0 PicoPHY IP is the first PHY IP to support the new Battery Charging Version 1.1 and USB On-the-Go (OTG) Version 2.0 specifications from the USB Implementer's Forum (USB-IF).
The Battery Charging v1.1 specification allows mobile devices to draw up to 1.8A of current when connected to a wall charger.
The Battery Charging specification enables portable devices to distinguish among various power sources, such as a wall charger, a standard host port and a USB charging port and selects the most efficient method to charge the device.
By supporting the USB OTG v2.0 specification, Designware USB 2.0 PicoPHY incorporates the Attached Detection Protocol (ADP) feature, which improves the power efficiency of portable devices that communicate directly to USB peripherals without the need for a PC host.
Designware USB 2.0 PicoPHY supports advanced power management features, such as power supply gating and support for ultra-low standby current to help designers lower the leakage power of mobile system on chips (SoCs) while maintaining the integrity of the USB 2.0 connection.
The Designware USB 2.0 PicoPHY IP is expected to be available to early adopters starting in the fourth quarter of 2009 for 28nm processes, with a roadmap for 40nm and 32nm.
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