Altera upgrades Quartus II design software
An Altera Europe product story
Edited by the Electronicstalk editorial team Nov 3, 2009
Altera Corporation has released Version 9.1 of the Quartus II software for CPLD, FPGA and Hardcopy application-specific integrated-circuit (ASIC) designs.
Features and enhancements within Quartus II v9.1 reduce compile times by 20 per cent compared to the previous software release, while delivering, on average, two to three times faster compile times compared to competing high-density 40nm and 65nm designs.
New to the software is the Rapid Recompile feature, which improves compile times for small design changes, as well as providing support for Altera's Cyclone IV FPGAs.
The software provides fast compile times for high-end FPGAs, averaging a 20 per cent reduction annually over the past five years.
The compile time advantages in the latest release are driven by more efficient place and route algorithms, improved multi-processor support and faster timing-driven synthesis.
The new Rapid Recompile feature enhances the Quartus II software's ability to further minimise design compilation times.
Rapid Recompile maximises designer productivity when making small engineering change order-style design changes after a full compile is run, reducing compilation times by 50 per cent on average versus running another full compile on the design.
It also improves designer productivity during timing closure by preserving critical timing during late design changes.
The three smallest Cyclone IV GX devices will be supported in the Quartus II v9.1 design software with the remaining Cyclone IV devices supported in the Quartus II v9.1 service pack 1.
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