Tensilica introduces Xtensa LX3 DPU core
A Tensilica product story
Edited by the Electronicstalk editorial team Nov 3, 2009
Tensilica has introduced the Xtensa LX3 high-performance dataplane processor (DPU) core, optimised for digital signal processing (DSP) and control in the system-on-chip (SoC) dataplane.
The Xtensa LX3 DPU offers a wide range of pre-verified DSP options, from a simple floating point accelerator to a 16 multiply accumulator (MAC) vector DSP powerhouse.
The base Xtensa LX3 DPU configuration can reach speeds of more than 1GHz in 45nm process technology (45GS), with an area of 0.037mm2 and power of 0.015mW/MHz.
When built with the new ConnX Baseband Engine DSP (ConnX BBE), the Xtensa LX3 processor delivers more than 10 Giga-MACs-per-second performance, running at 625MHz, with a footprint of 0.93mm2 (post place-and-route 45GS) and consuming 170mW (including leakage).
The Xtensa LX3 DPU has been fine-tuned with optimised scripts for the latest generation of EDA tools to deliver even better speed-power-area results than the predecessor Xtensa LX2 cores.
When comparing functionally equivalent configurations of the Xtensa LX3 DPU versus the prior-generation Xtensa LX2 DPU, the new Xtensa LX3 processor delivers a 15 per cent faster clock speed, a 20 per cent smaller die area and up to 15 per cent less power using identical process technologies and libraries.
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