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Design and Development Software
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Extended RTL-to-GDSII low-power reference design
Extended RTL-to-GDSII low-power reference design flow for the latest 65-nanometer (nm) process offered by the IBM-Chartered Semiconductor Manufacturing-Samsung Common Platform technology initiative.
News from Synopsys (21 July 2006)
Faster to market using Galaxy design platform
User application article Synopsys' Galaxy design platform provides a complete RTL-to-GDSII low-power solution that has enabled customers to develop more competitive products and get them to market faster
News from Synopsys (21 July 2006)
Low power methodology aids ARC designs
Azuro's PowerCentric low power methodology now is available for ARC licensees designing audio- or video-centric digital chips for embedded applications.
News from Azuro (21 July 2006)
Design and system interconnect go with the flow
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 7.0.
News from Cadence Design Systems (20 July 2006)
Interface brings harmony to microwave software
Vector Fields and AWR have completed the integration of Concerto software into AWR's Microwave Office circuit design platform.
News from Vector Fields (20 July 2006)
Alliance to aid multimedia chip designers
CoFluent Design is working with Sonics to reduce time to profitability of joint customers developing digital multimedia systems.
News from CoFluent Design (20 July 2006)
Software makes more of programmable platforms
The Programmable Synthesis Engine is a logic optimisation and mapping software product that is customisable for a variety of programmable platform architectures.
News from Softjin Technologies (20 July 2006)
Self-service demos show off software at DAC
Pulsic is offering visitors to this year's Design Automation Conference (DAC) in San Francisco an innovative way of learning what's new about its products and services.
News from Pulsic (20 July 2006)
Reference flow takes in more tools
Latest TSMC reference flow features a powerful statistical static timing analyser, a set of new power management techniques and an array of design for manufacturing enhancements.
News from TSMC (19 July 2006)
EDA tool suppliers join compliance programme
Multiple TSMC design service ecosystem partners have achieved DFM compliance for their 65nm tools.
News from TSMC (19 July 2006)
Software architecture management comes to Europe
Software architecture management specialist Lattix is moving into the European market in partnership with Scientific Computers, a leading systems integrator based in the UK.
News from Lattix (19 July 2006)
Virtual system prototyping majors on multicore
Comet6 extends Vast's lead in embedded systems design by providing the richest set of product enhancements to date.
News from Vast Systems Technology (19 July 2006)
Processor model aims to unite design flow
The 1-Source initiative aims to unify the embedded system design flow.
News from Vast Systems Technology (19 July 2006)
Timing analyser handles 20-million-gate designs
User application article NEC Electronics' EMMA project team has successfully taped out designs with up to 20 million gates using Incentia's TimeCraft static timing analyser and its advanced on-chip-variation analysis.
News from Incentia Design Systems (19 July 2006)
Matsushita joins investors
The world's largest consumer electronics company has made an investment in the Berkeley Design Automation through its venture group based in San Jose.
News from Berkeley Design Automation (18 July 2006)
Partnership programme aids SiP designers
Polyteda Software Corporation has set up its Initial Strategic Partnership Programme (ISPP).
News from Polyteda Software Corporation (18 July 2006)
Chartered is first to join partner programme
Chip Estimate Corp has set up its own a foundry partner programme, with Chartered Semiconductor Manufacturing as its founder member.
News from Chip Estimate Corp (17 July 2006)
Distribution deal is prelude to US office
CoFluent Design has taken the first steps towards establishing a direct presence in the US market.
News from CoFluent Design (17 July 2006)
Advisory board kicks off Liberty standard at DAC
Synopsys and the Silicon Integration Initiative (Si2) have named the founding members of the Liberty standard technical advisory board (TAB).
News from Synopsys (17 July 2006)
Clocking software cuts CSR chip consumption
User application article CSR has successfully taped-out its first design using Azuro's PowerCentric clock implementation solution.
News from Azuro (17 July 2006)
Diagnostics technology lead extended
Industry-award winning Cadence encounter test expands data compression and yield diagnostic offerings to address escalating manufacturing costs and yield ramp.
News from Cadence Design Systems (14 July 2006)
Taiwanese firm taps Celoxica ESL design
User application article Celoxica has announced an agreement with Chunghwa Picture Tubes that deploys its electronic system level design solutions to drive the development of volume HDTV and advanced display technologies.
News from Celoxica (14 July 2006)
Award for Design-for-Test Team
Mentor Graphics Design-for-Test Team Awarded IEEE CEDA Donald Pederson Best Paper Award.
News from Mentor Graphics UK (14 July 2006)
Next generation for data distribution
OpenSplice v2.0 provides a real-time information backbone, ensuring the right information is available in the right place at the right time
News from PrismTech (14 July 2006)
New partner for CMOS research platform
Micron becomes ninth core partner within IMEC's (sub)-32nm research platform.
News from IMEC (13 July 2006)
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