Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter and Allegro
Edited by the Electronicstalk Editorial Team on 20 July 2006
Design and system interconnect go with
the flow
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 7.0.
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 7.0 With this reference flow, which supports designs targeting TSMC's Nexsys 65-nanometre, process technologies, Cadence continues an established track record of innovation by improving its software for power optimisation and analysis, design for manufacturing (DFM), chip-package integration, and design for test (DFT)
This article was originally published on Electronicstalk on 10 Jun 2004 at 8.00am (UK)
Related stories
Platforms join new TSMC flow
Both the Encounter digital IC design platform and the Allegro system interconnect design platform have been integrated into TSMC's Reference Flow 5.0.
TSMC integrates nanometre design platforms
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's latest reference flow.
This latest milestone in the ongoing collaboration between the two companies delivers an RTL-to-package reference flow to accelerate time to volume for high-performance designs and low-power designs.
The flow delivers a comprehensive methodology to address complex design issues at 65 nanometres, such as tight manufacturing parameters, an exponential increase in leakage power, and new extraction requirements.
Within Reference Flow 7.0, Cadence technologies address these key issues by improving concurrent routing and dual-via inserti