News Release from: TSMC
Edited by the Electronicstalk Editorial Team on 19 July 2006

Reference flow takes in more tools

Latest TSMC reference flow features a powerful statistical static timing analyser, a set of new power management techniques and an array of design for manufacturing enhancements.

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Taiwan semiconductor manufacturing Company has introduced Reference Flow 7.0 that features a powerful statistical static timing analyser (SSTA), a set of new power management techniques and an array of design for manufacturing (DFM) enhancements. It also adds a Magma Design Automation design implementation track to the existing Cadence and Synopsys design tracks for easy adoption of TSMC's 65nm process technology. 'Extensive collaboration with our EDA design ecosystem partners has become the hallmark of TSMC's reference flows and this year is no exception', said Ed Wan, Senior Director of Design Services Product Marketing.

'Reference Flow 7.0 continues to lower design barriers for 65nm designs and provides a proven path to success'.

TSMC first opened the door for designers targeting 65nm process technology in 2005 with Reference Flow 6.0.

Since then, new tools and services have been integrated into the flow and validated on TSMC's industry leading 65nm technology.

TSMC Reference Flow 7.0 is the first foundry design methodology to include a statistical timing analysis capability to optimise design margins and die yields by accurately analysing the timing effects of manufacturing process variations.

Statistical timing analysis tools are from Cadence Design Systems, Synopsys and Magma.

Capabilities include statistical Spice models, library and IP characterisation, standard cell design kits, EDA tool enhancements and corresponding design methodologies.

'Synopsys and TSMC have been collaborating to address the challenges of 65nm IC design', said Antun Domic, Senior Vice President and General Manager of Synopsys' Implementation Group.

'One of the emerging requirements is to manage the uncertainty introduced by process variation'.

'Our statistical timing analysis and extraction solutions are a very significant extension of our widely deployed signoff tools, helping ensure accuracy and predictable silicon performance'.

'Together with many new technologies throughout our Galaxy Design Platform, including IC Compiler, we are delivering a comprehensive RTL-to-GDSII solution in the TSMC Reference Flow 7.0 today'.

'The integration of Quartz SSTA's statistical timing analysis capabilities in TSMC's Reference Flow 7.0 Magma IC implementation track is a technological breakthrough that will enable designers to address process variations in nanometre designs', said Kam Kittrell, General Manager of Magma's Design Implementation Business Unit.

'We're very pleased that our software is incorporated into the TSMC Reference Flow 7.0, which reinforces our commitment to working with TSMC to speed ramp up on 65-nm and lower process technology'.

Reference Flow 7.0 provides new dynamic and leakage power reduction tools, including an enhanced voltage island implementation and multiple-corner timing closure.

A coarse-grained power gating technique helps achieve leakage reductions of up to two orders of magnitude.

New power management libraries are also included.

'To keep the design intent, it is critical to verify and validate design functionality during various power-off states to achieve low dynamic power', said Jim Miller Jr, Executive Vice President, Products and Technologies Organisation at Cadence.

'TSMC and Cadence have collaborated to meet the low-power design challenge in the new reference flow'.

'Integrating low-power design methodology and power-management library improves designers' productivity and achieves project targets with reduced cycle time'.

Reference Flow 7.0 includes key DFM features that designers can exercise throughout the design cycle.

For example, critical area analysis (CAA) proactively identifies potential random manufacturing defects and drives wire spreading and wire widening corrective actions.

Virtual chemical mechanical polishing (VCMP) analysis identifies metal and dielectric thickness variation hot spot, and guides dummy metal insertion to improve thickness uniformity throughout the chip.

In addition, selected lithography process check (LPC) post-production tools have been qualified by TSMC as DFM compliant.

Reference Flow 7.0 includes a third implementation track partner, Magma Design Automation.

Similar to the implementation tracks featuring tool sets predominantly from Cadence and Synopsys, the new Magma track delineates a complete methodology using mostly Magma's tools.

The flow has been validated by TSMC and is available immediately.

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