SystemC synthesis is improved

Latest version adds features for significantly improving power results, automating design creation for synthesis from ANSI-C/C++ algorithms and implementing engineering change orders.

The latest version of the Cynthesizer SystemC synthesis product from Forte Design Systems adds features for significantly improving power results, automating design creation for synthesis from ANSI-C/C++ algorithms with high quality of results (QoR), and implementing engineering change orders (ECOs) for seamless integration with ASIC and SoC flows.

Cynthesizer 3.4 adds integration for Synopsys' Power Compiler, a key component of Synopsys' Galaxy Design Platform and Synopsys' comprehensive Eclypse Low Power Solution.

At the RT level, Power Compiler enables fast and efficient tradeoff analysis by performing automatic clock gating without requiring any changes to the RTL source.

Power Compiler further reduces power during synthesis optimisation by measuring tradeoffs between positive timing slacks, area, and power and producing the lowest power-consuming design that meets user-defined timing and area constraints.

Power estimation reports generated by Power Compiler are included in the results available in the Cynthesizer Workbench, Cynthesizer's graphical interactive analysis environment.

These reports, cross-linked to annotated source code views, make it easy to understand implementations tradeoffs and make changes for improved QoR.

Users can find all of the analysis information they need easily in one place.

According to Brett Cline, Forte's Vice President of Marketing and Sales: "Power is an important consideration for virtually every design today".

"Cynthesizer's silicon-proven quality of results for both datapath and control-based designs is now significantly enhanced with our integration with Power Compiler, as enabled through our membership in Synopsys' in-Sync Programme".

"Our customers are now able to easily make tradeoffs between area, power and performance".

The new Cynthesizer Interface Generator creates highly customised preverified interfaces for data ommunications between modules and threads in designs.

This greatly improves the process of converting single-threaded C++ algorithms to multithread or multimodule hardware architectures raising the abstraction level available to designers.

The Interface Generator supports several types of custom interfaces, such as streaming, circular buffers and shared memories.

Each interface itself can be customised in terms of its specific data type, capacity, synchronisation mechanism and other parameters.

This technology makes it very easy to build fully synthesisable data-transfer interfaces that are highly customised to designers' specific algorithms, resulting in efficient RTL quickly.

It also makes it easy to substitute different interfaces for different configurations, thus allowing exploration of the optimum system architecture system without recoding.

Cynthesizer's new RTL Viewer allows provides designers with a graphical view for examining the RTL generated from the behavioural source including the various parts, functions, and registers and how they interact with each other.

In addition, both SystemC and Verilog source can be viewed with annotations and links to the behavioural source as well as to other views available in the Cynthesizer Workbench.

This tight link between the original algorithm and the resulting RTL provides an easy way to understand the relationship between the RTL and the behaviour and to improve the quality of the RTL by applying various optimisation techniques.

ECOs can now be easily propagated from gates and RTL to the original SystemC source.

Cynthesizer v3.4 is available today from Forte.

All the new features are available at no additional charge to existing customers.

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