Evatronix seminars discuss Superspeed technology

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Edited by the Electronicstalk editorial team Nov 27, 2009

Evatronix has announced that it will will host a series of technical seminars on 2 December at the IP-ESC Conference in Grenoble, jointly with speakers from the industry.

The seminars will be available to everyone and a conference pass is not required.

The first seminar, 'The new kid on the USBlock; introduction to the Superspeed USB 3.0 technology' is a 30min technical seminar and will begin at 10am.

'USB 3.0 brought to the masses; how to build a USB 3.0 mass-storage application' will discuss the key benefits and techniques of developing such an application based on a Superspeed USB 3.0 peripheral controller.

This will take place at 10.30am.

'Choosing NAND Flash-based storage for your next project' will take place at 12.30pm and will discuss NAND Flash memory in embedded applications using SD, e-MMC and bare NAND Flash as an example.

'Superspeed USB 3.0 IP verification; where the marketing slogans end' will cover five directions an SoC designer may take while building a verification environment for his application.

The OCP infrastructure, RTL/TLM models, multi-layer verification environment, coverage-driven verification and formal methods for verification closure will be discussed and the seminar will start at 1pm.

'NAND Flash memories; current status and the future', to be delivered by Samsung Semiconductor NAND Flash memories division, will present the current situation in the NAND Flash market, as well as give an insight look into the future of this technology.

The seminar time will be 2pm and Samsung Semiconductor will also show the its latest achievements, as well as the roadmap for each of the Samsung NAND Flash products.

The High Speed Synchronous ONFi Interface, from Micron, will describe the features and key benefits of the ONFi standard for NAND Flash memories.

They will focus on the sychronous interface and provide an insight into the future of ONFi.

This will take place at 3pm.

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