TSMC Reference Flow 9.0 uses Powercentric CTS
An Azuro product story
Edited by the Electronicstalk editorial team Apr 6, 2009
Taiwan Semiconductor Manufacturing Company's (TSMC) Reference Flow 9.0 has incorporated Azuro's Powercentric clock tree synthesis (CTS) system.
Powercentric reduces clock power and area, and improves timing.
Reference Flow 9.0 is the latest version of TSMC's design methodology to lower design power, improve margins, and increase the yield of designs in its 40nm process technology.
S T Juang, senior director of design infrastructure marketing, TSMC, said: 'Azuro's Powercentric tool delivers significant power savings, and improves clock timing by reducing clock skew and insertion delay.' Powercentric removes productivity obstacles in the design flow by improving CTS automation and enabling designers to quickly comprehend and analyse the most complex interleaved clock networks.
'The inclusion of Powercentric in Reference Flow 9.0 follows from superior timing and power results that have been proven in silicon across several TSMC technology nodes,' said Paul Cunningham, co-founder and chief executive officer, Azuro.
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