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Product category: Microprocessors, Microcontrollers and DSPs
News Release from: Fujitsu Microelectronics Europe | Subject: CS101 Series SoCs
Edited by the Electronicstalk Editorial Team on 30 July 2003

SoC process shrinks to 90nm designs

Fujitsu has begun accepting orders for the CS101 Series of SoCs employing its state-of-the-art 90nm CMOS technology

Fujitsu was among the first in the industry to deploy 90nm CMOS technology, starting production at its Akiruno Technology Centre in December 2002. The company first used the technology in its own high-end products that demanded ultra-high-speed performance. The new SoC platform builds on the expertise developed at the Akiruno Technology Centre in 10-layer copper interconnects, Low-k insulating material, and other advanced technologies, making increased integration and reduced power consumption available for the SoC chips for digital consumer and mobile applications.

The CS101 Series achieves roughly double the level of integration of the company's existing CS91 Series of SoCs: up to 100 million gates, with the lowest power consumption in the industry, and a leakage current one-tenth that of the CS91 Series.

All these features make the new lineup especially well suited to mobile devices for which compactness and low power consumption are especially important.

With the adoption of Fujitsu's new SoC device, a mobile phone could offer six consecutive hours of talk-time and up to 1kh of standby time, and a credit card-sized digital camera could be miniaturised even further.

Fujitsu has a strong production track record in advanced process technologies combining copper interconnects and Low-k insulating material for its last two generations of system devices, 0.13um and 90nm.

Based on this proven record of reliability, Fujitsu is now making these technologies available to implement in SoC chips for digital consumer and mobile applications.

In addition to offering increased integration and functionality, Fujitsu can help customers cope with the problem of long, complex design cycles with its DesignExpress short TAT service, which can halve the time and steps required in design.

Fujitsu plans to extend the CS101 series with the addition of a high-speed interface for use in networking equipment, and will roll out products for an expanded range of applications starting next year.

Leakage current of the transistor is held to the lowest levels in the industry, cutting standby power consumption to roughly one-tenth that found in the company's existing devices, the CS91 Series.

When running at 1.2V, operating power consumption is 2.7nW (at one gate, 1MHz), roughly half that of earlier devices.

With a density of 420,000 gates per square millimetre, this design can accommodate up to 100 million gates per chip, roughly double that of its predecessor.

Each SRAM cell uses only 1.14um2, among the smallest in the industry.

Copper interconnects - up to ten layers of them - minimise resistance, and the use of low-k insulating material across the entire chip for reduced interconnect capacitance helps to minimise the impact on electrical characteristics.

Adopting a mixture of three different kinds of core transistors - low-leakage-current transistors, high-speed transistors and ultra-high-speed transistors - enables the SoCs to achieve the twin goals of low power consumption and high speed.

The gate delay time, which uses the high-speed transistors, is 12ps, about 70% faster than the CS91 Series of products.

To support a wide range of applications, which may require A/D and D/A convertors, PLLs, high-speed interfaces, low power consumption or high speeds, Fujitsu offers a range of fine-tuned macros.

Fujitsu provides physical prototyping for this platform.

By introducing this methodology, customers can reduce design time significantly.

And with Fujitsu's short TAT service DesignExpress, customers can design FPGAs and ASICs concurrently, reducing design time and steps in half.

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