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Design and Development Software
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Software supports structured ASIC design
eASIC has adopted two products from Golden Gate's GoPower suite Brochure available
News from eASIC Corp (8 June 2004)
Upgrade speeds synthesis and timing software
The latest versions of TimeCraft, DesignCraft and DesignCraft Pro feature improved runtime, capacity and quality, when compared with the 2003.09 release
News from Incentia Design Systems (8 June 2004)
Simulation helps provide cost-effective screening
User application article Electromagnetic simulation has substantially reduced the cost of the protective shields surrounding magnetic resonance imaging (MRI) suites at one Chicago hospital
News from Vector Fields (8 June 2004)
Compiler automates SystemC synthesis
The Agility compiler synthesises SystemC directly to high-density FPGA and programmable SoC logic and generates RTL VHDL and Verilog for SoC design
News from Celoxica (8 June 2004)
Investors consolidate support for Celoxica
Celoxica Holdings has raised $6.3 million of new investment from existing investors led by Advent Venture Partners, Cazenove Private Equity, Intel Capital and Quester Venture Capital
News from Celoxica (8 June 2004)
Software supports Spartan-3 designs
Altium is adding support for Xilinx Spartan-3 platform FPGAs to its Nexar system design software
News from Altium (8 June 2004)
Amino set for AIM flotation
Amino Technologies will float on the UK AIM on 9th June 2004
News from Amino Communications (7 June 2004)
Collaboration marries IC and package design
Ansoft is working with Synopsys to provide streamlined IC and package codesign and analysis design flow solutions
News from Ansoft Europe (7 June 2004)
Media processing speeds comms development
Aculab has integrated its range of media processing resources with the Envox 6 communications development platform
News from Aculab (7 June 2004)
Verification supports Accelera's PSL
A new version of Verix is now shipping with support for PSL - Accellera's property specification language
News from Real Intent (4 June 2004)
Floorplanner gains Java-based visualisation
Hier Design is to bundle Concept Engineering's NlviewJA Widget, a Java-based visual debugging software engine, into its PlanAhead hierarchical floorplanning and analysis software
News from Hier Design (4 June 2004)
Philips commits to Galaxy
Royal Philips Electronics has signed a new multiyear volume purchase agreement extending and expanding its deployment of the Synopsys Galaxy front-end design platform
News from Synopsys (4 June 2004)
Maths software boosts programmer productivity
The latest release of Matlab enhances programmer productivity with new tools that enable rapid, iterative program creation
News from The MathWorks (4 June 2004)
Model-based design extends to large-scale projects
Simulink 6 brings model-based design to complex projects encompassing large models and multiple design teams
News from The MathWorks (4 June 2004)
Tools work together to verify system level design
Cadence Design Systems has combined with CoWare to develop an integrated, seamless flow from electronic system-level design through verification for complex SoC designs
News from Cadence Design Systems (3 June 2004)
Platform adds support for Virage Logic libraries
Support is now available for both Virage Logic ASAP Logic structured-ASIC Metal Programmable and Standard Cell Libraries within the industry-leading Cadence Encounter digital IC design platform
News from Cadence Design Systems (3 June 2004)
Driver tools take on PowerPC on Linux
The WinDriver PCI/USB driver development tool now enables PowerPC based driver development for the Linux operating system
News from Jungo (3 June 2004)
Circuit simulation boosted twenty-fold
Synopsys has added significant performance enhancements and extended high-frequency design support in HSpice
News from Synopsys (3 June 2004)
M16C toolset gains speedier compiler
Version 3.0 of the Tasking M16C software development toolset has been enhanced with next-generation Viper compiler technology
News from Altium (3 June 2004)
Synthesis tool speeds C designs to RTL
Catapult C is billed as the only algorithmic synthesis tool that uses pure, untimed C++ to create quality RTL descriptions up to 20 times faster than traditional manual methods Brochure available
News from Mentor Graphics UK (2 June 2004)
New tool speeds Siemens code to RTL
User application article Siemens ICN has reduced C source to RTL implementation time by 50% on a strategic project using the new Catapult C synthesis tool Brochure available
News from Mentor Graphics UK (2 June 2004)
Automated functional analysis speeds verification
Periscope is an automated functional analysis solution claimed to significantly reduce time and effort spent in the verification process for complex systems on chip (SoCs)
News from Atrenta (2 June 2004)
IMEC to help with modelling extension
IMEC and Praesagus have signed a technology development agreement to extend Praesagus' physics-based modelling approach for pattern-based interconnect manufacturing variation
News from Praesagus (1 June 2004)
Software supports Freescale ColdFire processors
The Integrity RTOS is now available for the Freescale ColdFire MCF548x and MCF547x processor families Brochure available
News from Green Hills Software (1 June 2004)
Toolkit speeds data recording developments
A new data recording toolkit aims to ease the development of custom data recording applications, while reducing time to market and development costs
News from Vmetro-Transtech (1 June 2004)
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