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Design and Development Software
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Jivaro qualified for post layout simulation flow
Edxact announces that STMicroelectronics has added Edxact's Jivaro parasitic reduction tools to its Post Layout Simulation flow (PLS), in order to speed up simulations of back-annotated netlists.
News from STMicroelectronics (26 July 2006)
Automated Design and Implementation Flow
Cadence Design Systems and ARM have announced the joint development of the first automated RTL design and implementation flow for the ARM Cortex-A8 processor.
News from Cadence Design Systems (26 July 2006)
Mathworks introduces link for modelsim 2
Tool upgrade adds direct verilog support; collaboration with Mentor Graphics, streamlines verification process and enhances model-based design
News from The MathWorks (26 July 2006)
ProDesign releases chipit copper edition
ProDesign releases chipit copper edition at the 43rd DAC
News from ProDesign (26 July 2006)
Synopsys primeyield LCC links to IC compiler
Synopsys primeyield LCC links to IC compiler for automated correction of lithography problems
News from Synopsys (26 July 2006)
Statistical capabilities for primetime
Synopsys extends PrimeTime and Star-RCXT with statistical capabilities to address variation-aware design challenges
News from Synopsys (26 July 2006)
Analog fastspice and RF fastspice tools
Tools deliver Full-Spice Accuracy at 5x-10x Performance Without Tuning
News from Berkeley Design Automation (25 July 2006)
Ansoft joins Novas harmony partner program
Nexxim integrates with Novas' Verdi debug system for rapid viewing and exchange of verification results
News from Ansoft Europe (25 July 2006)
Help for system-on chip designers
Concept Engineering introduces SGvision Pro to help system-on chip designers analyse and debug mixed-mode circuits
News from Concept Engineering (25 July 2006)
Software set for San Francisco showing
UniqueICs company is preparing to take part in the Design Automation Conference (DAC) in San Francisco.
News from Unique ICs (24 July 2006)
Electrothermal software aids SoC reliability
Novel software assesses the effect of SoC temperature on leakage, timing, reliability and voltage drop.
News from Apache Design Solutions (24 July 2006)
Software suite supports requirements modelling
Artisan Studio 6.1 includes features and functionality in support of the new SysML standard.
News from Artisan Software Tools (24 July 2006)
DSP software accelerates implementation
Synplicity has enhanced its Synplify DSP solution to further accelerate the implementation of DSP algorithms into silicon.
News from Synplicity (24 July 2006)
Scan compression automation proves popular
User application article DFT MAX scan compression automation solution has been instrumental in reducing test costs related to data inflation on more than 50 successful tapeouts since its general release in September 2005.
News from Synopsys (24 July 2006)
Interoperable solutions speed customer development
IAR Systems and Micrium have signed a business agreement under the terms of which both companies will market and sell each other's products.
News from IAR Systems (21 July 2006)
Floating-point arithmetic toolkit
New toolkit for floating-point arithmetic implementation in high-density programmable logic.
News from Celoxica (21 July 2006)
Reference flow 7.0 includes design for test suite
Mentor Graphics' entire design for test tool suite is included in TSMC's Reference Flow 7.0.
News from Mentor Graphics UK (21 July 2006)
Bluetooth audio development with SBC middleware
Renesas introduces SBC Middleware, an important enabling tool in the development of audio applications for Bluetooth devices using SuperH family microprocessors incorporating an SH3-DSP CPU core.
News from Renesas Technology Europe (21 July 2006)
Embedded Linux webinars continue
TimeSys Corporation is beginning a new series of embedded Linux webinars in mid-July.
News from TimeSys Corp (21 July 2006)
Expression coverage aids verification performance
Expression Coverage for Verilog is included in the latest release of Riviera.
News from Aldec (21 July 2006)
Debug and simulate before silicon implementation
Arteris will output SystemC transaction level models (TLM) from its NoC tool suite for incorporation into TLM platforms developed in CoWare Platform Architect.
News from CoWare (21 July 2006)
Premier source for Japanese coverage
Pyxis Technology has signed Premier Technologies of Japan to represent it in the Japanese market.
News from Pyxis Technology (21 July 2006)
Multi-year OEM agreement with Eve
Synplicity has signed a multi-year OEM agreement with Eve pursuant to which Synplicity will provide Eve's customers with access to Synplicity's industry-leading FPGA synthesis technology.
News from Synplicity (21 July 2006)
Verification methodology proves popular
Industry adoption and support of the Verification Methodology Manual for SystemVerilog, co-authored by ARM and Synopsys, has steadily increased since the book's release in September 2005.
News from Synopsys (21 July 2006)
Platforms support 65nm reference flow
Synopsys' Galaxy design and DFM platforms support TSMC's Reference Flow 7.0.
News from Synopsys (21 July 2006)
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