Click on the advert above to visit the company web site
Product category: Design and Development Software
News Release from: Aldec | Subject: Riviera 2006.06
Edited by the Electronicstalk Editorial Team on 21 July 2006
Expression coverage aids verification
performance
Request your FREE weekly copy of the Electronicstalk email newsletter. News about Design and Development Software and more every issue. Click here for details.
Expression Coverage for Verilog is included in the latest release of Riviera.
Aldec, a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, has announced the addition of Expression Coverage for Verilog in the release of Riviera 2006.06 This addition significantly improves efficiency of the verification process and enables delivery of higher quality, more reliable designs
This article was originally published on Electronicstalk