Fifth-generation FPGAs boost speed and capacity

Xilinx has unveiled its new Virtex-5 family of domain-optimised field programmable gate arrays built on the industry's most advanced 65nm triple-oxide technology.

Xilinx has unveiled its new Virtex-5 family of domain-optimised field programmable gate arrays (FPGAs), built on the industry's most advanced 65nm triple-oxide technology, breakthrough new ExpressFabric technology and proven ASMBL architecture.

In a related announcement today, Xilinx announced initial shipments of the Virtex-5 LX platform with future platforms to roll out over the next 18 months.

Key design team innovations in process technology, architecture and product development methodology have led to unprecedented performance and density gains with Virtex-5 FPGAs - at speeds on average 30% higher and 65% increased capacity over previous generation 90nm FPGAs - while reducing dynamic power consumption by 35%, maintaining the same low static power and consuming 45% less area.

The Virtex-5 family represents the fifth generation in the award-winning Virtex product line for Xilinx.

Since its introduction in 1998, the Virtex Series has emerged as the industry's number one choice in high-performance FPGAs with over $4 billion in cumulative revenues.

Now more designers than ever will benefit from the inherent flexibility and cost advantages of Xilinx FPGAs, fueling further expansion for the company into the $22.4 billion high-performance segment of the total ASIC/ASSP/PLD market.

"By exploiting 65nm triple-oxide process along with the unique advantages of our ASMBL architecture and revolutionary new ExpressFabric technology, the Virtex design team has delivered the highest level of performance, density, feature integration of any FPGA on the market today", said Wim Roelandts, Xilinx Chairman, President and CEO.

"Increasingly at the heart of the system, our platform FPGAs are deployed in a myriad of applications ranging from networking and telecom infrastructure to wireless basestations and multimedia/video/audio applications".

"We're confident that the trend toward broad adoption of FPGAs in advanced system-level applications over traditional custom ICs will accelerate with delivery of our new Virtex-5 family".

Based on the successful ASMBL (advanced silicon modular block) architecture, the Virtex-5 family includes four domain-optimised platforms for high-speed logic, digital signal processing (DSP), embedded processing and serial connectivity applications.

Through the ASMBL architectural approach, Xilinx offers a greater selection of devices, enabling customers to select the right mix of features and capabilities for their specific design.

As with the Virtex-4 family, customers can choose from a variety of Virtex-5 device options within each platform for the optimal mix of features to match end product requirements.

Initial devices of the Virtex-5 LX Platform are shipping now with each of the remaining platforms slated for the second half of 2006 through the first half of 2007.

Given the inherent performance and flexibility advantages of its new Virtex-5 family and the Company's historical strength in communications, Xilinx is poised to play a pivotal role with its customers in enabling the next wave of the Internet - the convergence of voice, video, and data on the same network, widely known as "triple play".

In anticipation of growing consumer demand for new mobile and residential services, revitalisation of today's network infrastructure has become a global electronics industry imperative.

This trend will afford semiconductor companies a tremendous growth opportunity across a wide range of end market segments, including wired/wireless communications, consumer, audio-video broadcast, storage and servers, and test and measurement.

Experts agree that "triple play" is likely to drive a spike in demand for high-performance platform FPGAs, given their adaptability to evolving consumer requirements, changing industry standards, time to market and cost pressures, and the need to future-proof systems.

"Bandwidth aggregation requirements are expected to increase 10-fold or more, ultimately requiring 20-50Mbit/s per channel in order to deliver these new services", said Bob Wheeler, Senior Analyst at The Linley Group.

"High performance programmable solutions such as the Virtex-5 family will play a key role for packet processing and transport in this communications infrastructure overhaul".

According to Alan Varghese of ABI Research: "Future SoC solutions must combine flexibility with very high-performance DSP, processing and connectivity capabilities in order to meet the aggregation bandwidth requirements of transporting voice, video and data".

"An example of such a solution is the Xilinx Virtex-5 family, which positions the Company well to expand its reach into these upcoming market opportunities".

Ultimate System Integration Platform Meets Stringent Customer Requirements Xilinx engaged with hundreds of system designers worldwide to define its next-generation Virtex-5 product line and to build key features into each platform that address designers' need for higher performance, lower power, high-bandwidth interfaces, lower system cost and shorter design cycles.

Among the key innovations of the Virtex-5 family available with the Virtex-5 LX Platform include the following.

The industry's first look-up table (LUT) with six independent inputs and a new diagonal interconnect structure reduces logic levels and improves signal interconnect between building blocks, resulting in an average increase of logic performance of 30% over the previous Virtex-4 generation.

Further, the new 65nm fabric improves logic utilisation by implementing functions in 45% less die area and reduces dynamic power.

Other enhancements and new hardened IP blocks tuned to 550MHz include larger 36Kbit dual-port BRAM/FIFO blocks with ECC option for higher on-chip memory bandwidth, clock management tile (CMT) with PLLs in addition to DCM/PMCD for highest quality clocking, and a new DSP48E block with enhanced multipliers for high-precision, high-performance signal processing.

Second-generation Sparse Chevron packaging technology enables designers to use up to 1200 user I/Os, supporting 1.25Gbit/s double datarate and 800Mbit/s single-ended with highest signal integrity, lowest system noise, while simplifying printed circuit board (PCB) layout.

Second-generation ChipSync technology, available in every I/O, is also enhanced for improved dynamic field recalibration of clock/data in source-synchronous interfaces.

Combined, these I/O technologies ensure reliable operation for high-bandwidth interfaces such as DDR2 and QDR II.

With a 1.0V core and reduced internal capacitance on 65nm fabric, Virtex-5 devices reduce dynamic power by 35% compared with previous generation devices.

By balancing performance and power with the unique triple-oxide technology, Virtex-5 FPGAs defy the industry trend of increased leakage at smaller process geometries by maintaining the low static power of its previous 90nm generation.

The ExpressFabric and power-saving modes in hard IP blocks further reduce power consumption.

These capabilities help designers meet their power budgets to prevent thermal runaway and reduce the need for heat-sinks and fans.

The Virtex-5 family provides 65% more logic cells (330,000 LCs) and 25% more user I/Os (1200 I/Os) compared with previous generation FPGAs.

With access to four domain-optimised platforms including a wide range of devices, customers will pay only for the capabilities needed.

New Serial Peripheral Interface (SPI) and byte-wide peripheral interface (BPI) configuration modes for support of low-cost commodity flash memory further reduce system cost.

Designers can achieve FPGA performance goals quickly with ISE Fmax technology, PlanAhead design analysis software and pre-verified IP cores, and also cut their debug cycle time with the advanced verification and real-time debug capabilities of ChipScope Pro tools.

Additional online resources, training courses, premium support services, and a worldwide network of Xilinx Design Services (XDS) will ensure that projects are finished on time.

Based on the vast partner ecosystem developed through nearly a decade of Virtex Series innovation, Xilinx has collaborated closely with partners to produce design tools and evaluation boards specifically designed to optimise the new features of the Virtex-5 architecture.

Delivery of new Virtex-5 family FPGAs has commenced with the availability of the initial LX devices, and will continue through the first half of 2007.

Early access software for Virtex-5 FPGAs is available now, with general availability in June 2006.

The Xilinx EasyPath programme, which offers an additional risk-free cost-reduction of up to 75% for high volume production, will be available to customers for each Virtex-5 platform on volume production.

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