Renesas adds the SH7205 to the SuperH range

Renesas Technology has introduced the SH7205 dual core microcontroller for consumer and industrial applications.

It can be used in digital audio/visual, office automation, factory automation and any other systems requiring connectivity, motor control functionality and high performance.

The SH7205 incorporates two SH-2A cores, each of which has an operating frequency of 200MHz and yields 480DMIPS.

This means a peak performance of 960DMIPS can be achieved from a single device.

The device also features two single/double-precision floating point units (FPU).

Engineers that develop algorithms on PCs using high-level abstraction tools require a microcontroller with a FPU.

Without a FPU, algorithms slow down significantly when the application is moved from the PC to an embedded platform.

The SH7205 has two Can channels for standard industrial communications, a USB module supporting up to high speed function or host, and six channels of serial communication interfaces (SCI), two channels of synchronous serial communication units (SSU) and four channels of IIC.

The device is fitted with RGB input and output and a 2D graphics engine to support visualisation applications.

It includes acceleration functions such as bit blitting, variable blending and font expansion as well as several resizing functions.

The device offers a MTU2 timer unit with five channels of 16-bit timers, support for up to 18 input capture/output compare functions and a three-phase PWM capability for electrical motors.

Additional motor control features are enabled by a quadrature encoder feedback capability.

The MTU2 incorporates additional safety features with its Port Output Enable (POE) pins that provide a faster and more deterministic response time to ensure quick shutdown of the motor.

The IC includes an eight channel ADC with 10-bit resolution.

The ADC can be triggered by the MTU2 with an additional defined delay time to support algorithms such as a single-shunt motor drive.

The internal bus system uses a CPU-specific multi-layer structure.

This four-layer configuration provides two layers for CPU use and two for DMAC (direct memory access controller) use.

This approach prevents time from being wasted while the bus is in use by the other CPU.

This aids high-speed real-time processing.

The cores can operate on different operating systems (OS) or the same one.

For example, if one CPU core runs a RTOS while the other runs the Clinux OS, they can execute completely different programs.

This capability lets engineers construct a system flexibly according to its use or purpose.

The two CPU cores can communicate directly with each other.

Each CPU can check the status of the other one and they can exchange data using memory provided for that purpose.

This means processing linkage can be implemented between the CPUs through mutual exchanges of their respective processing states and data.

The SH7205 features a 32-bit external bus interface for fast access to external memories.

It also features 96kB of internal user Ram as well as 2x16kB cache blocks, one for each core.

The IC includes a real time clock and supports up to 14 channels of DMA.

The SH7205 is available in a compact (17 x 17mm) 272-pin BGA.

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