Maco cores get buffer management

Lattice Semiconductor has announced that its LatticeSCM FPGA family-based SPI4.2 Maco (masked array for cost optimisation) cores have been enhanced by adding link layer buffer management options.

These features provide designers with a programmable buffer manager capable of: up to 16 separate physical FIFOs per TX/RX direction; packet overflow and error drop; store and forward as well as cut-through operation; programmable buffer depth and thresholds; dynamic channel provisioning; programmable sequencer-based scheduler.

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