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Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter and Allegro
Edited by the Electronicstalk Editorial Team on 9 June 2004

Platforms join new TSMC flow

Both the Encounter digital IC design platform and the Allegro system interconnect design platform have been integrated into TSMC's Reference Flow 5.0

This reference flow includes key Cadence technologies for low power design and chip-package design that enable higher productivity and improved design quality. Supporting designs targeting TSMC's 90nm process technology, the reference flow is the latest milestone in the long-standing design chain collaboration between TSMC and Cadence.

"TSMC and Cadence have been collaborating closely to provide complete design solutions available for our mutual customers", said Edward Wan, Senior Director of Design Services Marketing for TSMC.

"TSMC Reference Flow 5.0 delivers a comprehensive offering that uses advanced Cadence solutions to address critical 90-nanometre issues such as power closure and IC package optimisation".

"The result is a methodology that manages nanometre-scale design issues while delivering faster time-to-volume for low-power and high-performance designs".

TSMC Reference Flow 5.0 addresses critical nanometre design needs of power optimisation and power integrity through the Cadence Encounter platform, with power techniques such as low power synthesis, multiple supply voltages and power domains, leakage power optimisation, multiple supply voltages, automatic power grid generation, and IR (voltage) drop analysis.

This reference flow addresses low power design concerns, from prototyping through power/timing/area optimisation, and delivers improved timing closure, reduced device area and lower power consumption for complex multi-million-gate system-on-chip (SoC) designs.

These SoCs are typically used in advanced wireless and communications end markets.

The customer benefits are clear; increased productivity and optimised power consumption.

TSMC Reference Flow 5.0 includes Cadence Fire and Ice QX to provide accurate, full-chip, cell-based, 3D parasitic extraction for signal integrity, timing, and power analysis.

Cadence VoltageStorm is included with enhanced gate-level dynamic analysis.

This is especially important for 90nm and smaller processes where a tradeoff between dynamic loads and power grid decoupling becomes critical.

The reference flow's low power solution also includes Cadence Encounter RTL Compiler, Cadence First Encounter, Cadence Encounter Nanoroute and Cadence Encounter Celtic NDC.

"We use Cadence Encounter software to design leading-edge system-on-chip ICs, fabricated in TSMC silicon", said Scott Sellers, Vice President of Hardware Engineering, CTO and cofounder of Azul Systems.

"The collaboration between TSMC and Cadence has directly helped us to improve chip performance, particularly in the libraries and timing flows where we have done successful joint work together".

"We applaud the release of Reference Flow 5.0".

IC packaging is a critical factor in nanometre design.

TSMC has included Cadence Allegro Package Designer in Reference Flow 5.0 to address the emerging chip I/O and flip-chip challenges.

Allegro Package Designer enables customers to achieve collaborative design of high-performance interconnect across the domains of IC, package and PCB.

This cross-domain capability helps customers by supporting feasibility analysis and design of the IC's bump array or die pads in the context of the package interconnect.

This optimisation across domains reduces costs and accelerates time-to-market.

The Allegro platform also supports a co-design methodology that promotes collaboration across the entire system design chain.

By providing a common constraint-driven flow across design entry, signal and power integrity and physical design, it comprehensively addresses the implementation of system interconnect in nanometre designs.

"TSMC's leading process technologies drive many advanced flow requirements, and we are pleased to see the Encounter and Allegro platforms adopted as key components of the TSMC Reference Flow 5.0", said Lavi Lev, Cadence Executive Vice President and General Manager.

"The ongoing collaboration between Cadence and TSMC continues to address the most critical design risks for complex, multi-million-gate SoCs and enables customers to achieve first-pass silicon success".

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