Click on the advert above to visit the company web site

Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial Team on 8 April 2004

Reference methodology supports
speedy new cores

Cadence Design Systems and MIPS Technologies have developed an optimised MIPS-Cadence Encounter Reference Methodology for customers of MIPS32 24K cores

Cadence Design Systems and MIPS Technologies have developed an optimised MIPS-Cadence Encounter reference methodology for customers of MIPS32 24K cores, which is the embedded industry's highest performing 32bit synthesisable core family available for licensing. Available to customers of the 24K core family, the optimised Encounter digital IC design platform delivers superior performance and ease-of-use to MIPS-based SoC designers by incorporating the SoC Encounter RTL-to-GDSII system and Encounter RTL compiler synthesis with the support for a generic 130nm process.

At nanometre geometries, SoC performance is dominated by the timing and noise behaviour of a chip's routed wires.

The Encounter Reference Methodology optimised for the 24K core family provides an integrated, wire-centric RTL-to-GDSII core implementation for customers, fulfilling the objective to optimise the silicon design chain by providing better quality of silicon (QoS).

The Encounter platform integrates best-of-breed technology for wire-centric design with RTL Compiler synthesis, First Encounter for silicon virtual prototyping, NanoRoute nanometre router technology for signal integrity (SI) aware routing, and CeltIC SI and VoltageStorm tools for signal integrity signoff.

This reference methodology enables customers to achieve improved QoS, the new metric of silicon quality measured after wires for accuracy.

"As MIPS Technologies pushes the limits of performance in synthesisable microprocessor technology, it's important that we ensure customers have the technologies with which to meet their design goals quickly", said Victor Peng, Vice President, Engineering, MIPS Technologies.

"By working closely with Cadence on the 24K reference flow, we have enabled our customers to produce hardened 24K databases that achieve high frequencies and small die areas with reduced runtimes".

"We are pleased with the role of RTL Compiler global synthesis technology in optimising the silicon design chain.

The results of our teamwork with MIPS Technologies enables us to provide our mutual customers with a predictable path from RTL to better first silicon.

This new MIPS-Cadence Encounter Reference Methodology for use with 24K cores can eliminate weeks from our customers efforts to implement 24K core designs", said Dr Chi-Ping Hsu, Corporate Vice President, Synthesis Solutions, Cadence Design Systems.

"The Artisan Sage-HS Libraries are specifically designed for high-performance consumer electronics", said Neal Carney, Vice President of Marketing at Artisan.

"We are pleased that Artisan libraries were chosen to help launch the high-performance core and the MIPS-Cadence Encounter 24K reference methodology".

In order to achieve high QoS with an industry-standard design flow, MIPS Technologies is using the Encounter platform's wires-first methodology and best-of-breed technologies, such as Encounter RTL Compiler and the SoC Encounter RTL-GDSII system.

The SoC Encounter system offers integrated silicon virtual prototyping, physical implementation, SI-aware routing and signal integrity technologies for nanometer designs, like the 24K core design.

The Encounter RTL Compiler system replaces traditional design flows with a new design strategy that minimises time-to-wires and full-chip iteration time.

Encounter RTL Compiler provides a higher level of QoS by measuring a design's physical characteristics in terms of area, performance, and power - using wires.

The technology behind Encounter RTL Compiler synthesis delivers global optimisation for timing closure using a set of global algorithms that produce outstanding results at each stage of implementation, including a better starting point for routing complex, wire-centric designs.

The Encounter RTL Compiler is used throughout the silicon design chain by application-specific integrated circuit (ASIC) and intellectual property (IP) vendors, and IC designers to help increase overall chip speed.

It can also help to reduce turnaround time.

MIPS Technologies is offering customers of the 24K core family the Cadence Encounter platform reference methodology with the relevant synthesis scripts and floor planning information.

Support for the reference methodology is provided by MIPS Technologies.

• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• NEW
• Electronicstalk Home Page

Search the Pro-Talk network of sites

Put your news on Electronicstalk  |   Advertise  |   Get the free Electronicstalk newsletter
Electronicstalk Home  |   About Electronicstalk  |   Copyright © 2000-2007 Pro-Talk Ltd, UK