Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial Team on 01 June 2007
Design platform enable DDR integration
at 65nm
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform.
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform This new methodology uses Cadence SoC Encounter RTL-to-GSDII system for design and physical implementation and Cadence Encounter Timing System for design closure and final timing, signal integrity and signoff - both are key technologies of the CPF-enabled Encounter platform
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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