Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial Team on 5 October 2005
Design platform eases migration
from 90 to 65nm
The Cadence Encounter digital IC design platform has helped Silicon and Software Systems (S3) to successfully tape out a new production 65-nanometre design
The 500MHz consumer computing device, designed under contract for a major European customer, will be manufactured in a leading European 65-nanometre silicon wafer fab and is expected to reach very high production volumes. To help implement this and other 65-nanometre test-chip and subblock designs, S3 leveraged the complete Encounter RTL-to-GDSII flow, and applied its proven methodologies and approaches to solve the complex challenges of nanometre process design.
This article was originally published on Electronicstalk on 5 October 2005 at 8.00am (UK)
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This included building an automated environment for 65-nanometre mixed-signal design flow with RTL synthesis, virtual prototyping, physical synthesis, routing, signal and power integrity analysis, and 3D extraction.
This scripted design flow enabled fast design migration, regression turnaround time, rapid timing and signal integrity closure, high-speed digital, and mixed-signal routing to ensure high quality results in an evolving technology context.
'Moving from the 90- to The 65-nanometre node offered our customer significant advantages in die area and performance, and our advanced implementation flow helped control leakage power and other potential manufacturability challenges with the silicon', said Dermot Barry, General Manager of the System IC Business Unit at S3.
Further reading
Design flow overcomes lithographic limitations
Cadence Design Systems has created a lithography-aware design flow and has defined an interface that will link resolution enhancement technologies with physical design and verification
Platform enables early array signoff
Toshiba Corporation and Toshiba Microelectronics Corporation have successfully taped out the first UniversalArray chip with Cadence Encounter digital IC implementation
'The integrated Encounter RTL-to-GDSII flow allowed us to quickly and easily exercise multiple 'what-if' scenarios and revisions of our design as the library matured and new requirements were added'.
'This allowed us to provide our customer with the best quality of silicon possible in the shortest amount of time'.
'With this implementation flow, S3 is fully operational at The 65-nanometre node and we are taking new designs now'.
S3 provides outsourcing solutions to semiconductor and system companies at the leading edge of system IC design.
It provides a complete system IC capability from specification to tape-out and has an excellent first-time right track record.
'Building on its leadership position at 90 nanometres, S3 has clearly demonstrated its capability to migrate complex designs to the 65-nanometre technology node', said Wei-Jin Dai, Corporate Vice President, R and D for Cadence.
'We continue to be impressed with the excellent engineering team at S3 and are proud that they have chosen Encounter as their standard leading-edge synthesis and implementation solution'.
'Once again, Encounter is recognised as essential technology by an important customer'.
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