Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "RTL compiler", and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest. Let me be your guide.
Start with the news release Reference methodologies speed ARM design from Cadence Design Systems, which we summarised at the time by saying "Methodologies for two ARM processors provide enhanced design solutions to mutual customers designing multicore, low-power devices". A few weeks before, we featured the news release Multicore design optimises ARM performance from Cadence Design Systems: "Design success prompts NEC to standardise on the Encounter platform as its tapeout methodology of choice for ARM processor implementations".
In July 2007, we covered the news from Cadence Design Systems concerning its Logic Design Team Solution - take a look at Logic designers get physical with floorplan data which says: "'Design with physical' approach automatically delivers an accurate physical description of the design into the logic design stage".
Take a look also at the news release from Cadence Design Systems, Timing system is integral part of tapeout success, as well as 65nm reference flow targets Common Platform from Cadence Design Systems, and Compiler improves timing on large ASIC blocks from Cadence Design Systems.
See also:
IBM signs up for 65nm ASIC support (November 2006)
Cadence Design Systems has signed an agreement to incorporate Encounter RTL Compiler global synthesis and Encounter Test technologies into the IBM 65nm ASIC design kit
Design and system interconnect go with the flow (July 2006)
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 7.0
News on the Encounter RTL Compiler from Denali Software (June 2006)
Cadence Design Systems has announced support for Cadence Encounter RTL Compile