Optical interfaces boast top bandwidth

FPGA-based designs accelerate the design cycle of wired networking systems that require OC-192 (10Gbit/s), multiple OC-48 (2.5Gbit/s) or 10Gbit/s Ethernet interfaces.

Xilinx has developed complete solutions for the Optical Internetworking Forum (OIF) System Packet Interface (SPI) 4.2 and SerDes Framer Interface (SFI) 4.1 standards, the industry's highest performance channelised packet interfaces.

Based on its industry-leading high-performance Virtex-5 LXT FPGAs, the solutions feature the ML550 hardware verification board, SPI-4.2 LogiCore IP and SFI-4.1 reference design.

Verified across multiple FPGA platforms, the solutions accelerate the design cycle of wired networking systems that require OC-192 (10Gbit/s), multiple OC-48 (2.5Gbit/s) or 10Gbit/s Ethernet interfaces, resulting in much faster time to market than competing solutions.

"High-speed standards such as SPI-4.2 and SFI-4.1 are used in demanding applications that require proven silicon, reliable and precise data capture, IP cores and simple integration", says Anil Telikepalli, Senior Manager of Platform Solutions Marketing at Xilinx.

"Our field-tested and hardware-verified Virtex-5 FPGA solutions for SPI-4.2 and SFI-4.1 dramatically reduce design risk while providing the highest bandwidth".

The Xilinx ML550 board is ideal for development and evaluation of OIF and other networking interfaces, allowing designers to implement high-speed applications with extreme flexibility.

Xilinx unique ChipSync technology, available only in Virtex-5 FPGAs, provides accurate dynamic alignment of clock and data using 75ps programmable delays, enabling improved timing and reliable operation under changing system conditions.

The Xilinx SPI-4.2 LogiCore IP, which is fully compliant with the OIF SPI-4.2 standard, interconnects physical layer ASSPs to link layer FPGA devices in a wide range of networking applications and multi-service DWDM and Sonet/SDH-based transport systems.

The Xilinx SPI-4.2 IP core provides proven interoperability with industry leading ASSPs and provides up to 20% higher data bandwidth due to optimised payload efficiencies as compared with competing FPGA offerings.

The Xilinx SFI-4.1 reference design supports up to 710Mbit/s per channel with dynamic alignment to provide a robust solution for OC-192 framer interfaces The SFI-4.1 reference design is immediately available free of charge.

The SPI-4.2 LogiCore IP is available for a free evaluation and can be purchased for a US $18,000 site licence fee.

The Virtex-5 LXT FPGA ML550 board is available for US $2200.

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