Product development system makes more of FPGAs

The latest version of Altium's unified electronic product development system strengthens support for FPGA-PCB codesign and allows engineers to make full use of FPGAs as a system platform.

Altium Designer 6.0, the latest version of Altium's unified electronic product development system, significantly strengthens support for FPGA-PCB codesign and allows engineers to make full use of FPGAs as a system platform, and simplify the integration of large-scale FPGAs with the physical PCB platform.

Although the benefits FPGAs bring to logic development have long been recognised, the challenges associated with incorporating these devices into the PCB design flow can complicate the board design and lead to blow outs in overall design time.

FPGA pin assignments are often done without regard to board layout, and the dense packaging technologies used in large-scale programmable devices can make board routing a significant challenge.

Altium Designer eliminates the barriers to FPGA usage by unifying the design of the hard-wired PCB platform with the development of the software and soft-wired logic that make up the embedded intelligence that is programmed onto the board to create the complete application.

Altium Designer 6.0 strengthens integration between FPGA- and PCB-level design with a raft of new features that have been developed to streamline product development with today's large-scale programmable devices.

"The ready availability of large-scale FPGA devices is changing the way engineers approach system design - they allow more intelligence to be added to products while shortening design time and lowering production costs", said Nick Martin, founder and CEO, Altium.

"Altium Designer 6.0 allows engineers to take full advantage of the benefits FPGAs have to offer, both at the embedded intelligence and physical design levels".

"The unified nature of the system eliminates the barriers to the widespread adoption of programmable devices in mainstream design, and makes it possible to fully utilise the extensive resources of these devices to simplify both the logical and physical design challenges".

Altium Designer 6.0 introduces the concept of dynamic net reassignment that allows FPGA pins to be swapped on-the-fly during PCB routing.

This includes the dynamic reallocation of prerouted subnets and the swapping of linked differential signal pairs that make use of the LVDS resources abundant on FPGA devices.

Dynamic net reassignment combines with a significantly enhanced automatic FPGA pin optimisation engine to allow engineers to make full use of the FPGA pin reprogrammability to achieve optimum routing solutions at the board level.

The unified nature of the Altium Designer system allows pin changes made at the board level to be automatically synchronised with the FPGA project, eliminating time-consuming manual I/O management.

High-pin-count FPGA devices typically come in dense BGA-style packages.

This can cause difficult debugging problems at the prototype stage because the pins on these devices cannot be probed directly.

Altium Designer's LiveDesign development methodology allows an engineer to interact directly with their FPGA-based design during development.

Altium Designer 6.0 includes an enhanced JTAG device viewer that provides a graphical display of the pin status of all JTAG devices in a system that allows engineers to monitor pin signal status in real-time during debugging.

Pin status can also be dynamically displayed on both the source schematics and the PCB layout, allowing "in-place" viewing of signal status within the design documents.

This, combined with Altium Designer's FPGA-based virtual instruments, which are used to set and monitor signals inside the FPGA, gives designers a complete picture of the operation of their circuit and allows both logical and physical debugging of the system.

Live testing of an FPGA-based system has been strengthened in Altium Designer 6.0 with a significantly enhanced configurable logic analyser (LAX) virtual instrument.

The configurable LAX can monitor buses from 8 to 64bit width within an FPGA, and supports the connection of multiple signal sets.

Any signal set can be used to trigger a capture, and selected as the data source.

When the configurable LAX is connected to a processor instruction bus, the bus data can be displayed as disassembled code instructions, allowing code-dependent issues to be easily tracked in the LAX output.

Working with FPGA-based 32bit processor systems has also been made more versatile in Altium Designer 6.0 with addition of support for a range of third-party soft and discrete processors, including the Xilinx MicroBlaze soft processor, Sharp BlueStreak LH79520 (based on the ARM720T) and AMCC PowerPC 405CR discrete processors.

This adds to the 8 and 32bit target-independent soft processors already supplied with the Altium Designer system, and gives designers more flexibility in the development of embedded systems using FPGAs.

FPGA-based wrapper cores supplied in Altium Designer 6.0 allow designers to target supported third-party processors, while retaining the full design functionality of the Altium Designer environment, including the easy connection of FPGA-based peripherals and LiveDesign debugging using Altium Designer's virtual instruments.

Altium's Viper-based compiler tool chains maintain software compatibility between all processors, and the wrapper cores provide hardware compatibility.

This means embedded designers can easily migrate designs between processors without incurring significant re-engineering penalties.

Altium Designer 6.0 is available for purchase through all Altium's sales and support centres worldwide.

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