Product category: Design and Development Software
News Release from: Synopsys | Subject: Design Compiler
Edited by the Electronicstalk Editorial Team on 29 May 2007
Topographical technology speeds
cameras to market
Casio has adopted Synopsys Design Compiler topographical technology to shorten the design schedule for its next generation Exilim digital camera chips
The ever decreasing shelf life of consumer electronics products poses serious challenges for Casio's design engineers, whose key to success lies in bringing their next generation cameras to market faster and cheaper. Design Compiler topographical technology provides accurate information about chip performance early in the design process, creating a predictable design cycle that allows Casio designers to discover and fix design issues during synthesis for much faster design closure.
This article was originally published on Electronicstalk on 29 May 2007 at 8.00am (UK)
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Known for their stylish, slim looks, Casio's Exilim cameras feature high performance image processing chips for high picture quality and high speed picture shooting.
In the past, Casio designers had built pessimism into the timing parameters to ensure design closure, which resulted in larger silicon area.
Topographical technology's accuracy of results eliminates the need for this timing pessimism and enables a drastic 17% reduction in Exilim chip area, representing a significant savings in chip cost.
'The Exilim series of digital cameras is our most popular camera line, employing the latest digital technologies'.
'We are constantly looking at ways to cut both time to market and cost of designs in the highly competitive consumer electronics space', says Kazuyuki Kurosawa, Section Manager in the QV digital camera Unit at Casio.
Further reading
Korean chip designers get it right first time
ETRI has used Synopsys Design Compiler topographical technology to expedite the tapeout of its new 90nm multimedia chip
Synthesis tool accelerates microdisplay design
Displaytech has used the Design Compiler synthesis tool in designing its next-generation FLCOS backplane for high-resolution high-speed microprojection and holographic data storage systems
Acquisition harnesses mixed-signal verification
Sandwork's products, combined with Synopsys' industry leading Discovery AMS solution, deliver a comprehensive environment for verification and debug
'We have adopted Synopsys' Design Compiler topographical technology for our next generation designs'.
'Not only does it offer a predictable design flow for a shorter design cycle, but it also helps lower costs by reducing chip area'.
Design Compiler topographical technology shares technologies with the Galaxy Design Platform physical design solution to accurately predict chip performance results such as timing, area, testability and power consumption during synthesis.
Using Synopsys' topographical technology, front end designers can foresee layout results and take corrective measures to ensure that their design will achieve the required performance prior to sending the design to an ASIC vendor for implementation.
Consequently, the ASIC vendor receives a better starting point that speeds up implementation while meeting the required performance targets.
By reducing time consuming iterations between the ASIC customer and the vendor to close on design goals, Design Compiler topographical technology accelerates the design cycle.
'Customers such as Casio are telling us that global consumers are aggressively driving down both the schedule and cost of electronic products', says Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.
'Growing numbers of customers are adopting Design Compiler topographical technology to help complete their designs faster, with higher predictability and more cost effectiveness'.
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