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Product category: Design and Development Software
News Release from: Synopsys | Subject: Design Compiler
Edited by the Electronicstalk Editorial Team on 14 December 2006
Topographical technology in new 65nm
methodology
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Semiconductor Technology Academic Research centre has deployed Synopsys Design Compiler topographical technology in its 65nm Synopsys Galaxy Design Platform-based design flow
Synopsys has announced that the Semiconductor Technology Academic Research centre (STARC) has deployed Synopsys Design Compiler topographical technology in its 65nm Synopsys Galaxy Design Platform-based design flow (project name: Eagle Flow) in the Starcad-CEL methodology Topographical technology accurately predicts post-layout design performance such as timing, power, and area early in the design cycle, enabling designers to identify and fix issues during RTL synthesis
This article was originally published on Electronicstalk