Achieving next generation memory densities today

Chip-on-chip stacking technology can help designers achieve the highest possible electrical functionality and performance in the least possible amount of space.

As a result of miniaturisation and performance trends, designers are constantly looking for achieving highest possible electrical functionality and performance in the least possible amount of space.

In any processor based system from embedded applications to general purpose personal computers, DRAM, Flash memories and SRAM are used for execution, storage and caching of information, respectively.

As such, there are opportunities to reduce overall system constraints by offering chip-on-chip stacking applied to all these memory components as a way to save board space and achieve system performance goals.

Specifically, stacking technology is the mechanical and electrical assembly packaged components for the purpose of increasing depth, width, and/or functionality of electronic designs limited in surface area.

The chip-on-chip stacking implementation is the most cost-effective way of installing stacked packages on top of each other.

The same commercial manufacturing and test equipment is used to manufacture the stacked parts, modules, or cards based on this stacked solution.

The most popular chip-on-chip stacks are dual and triple stacks primarily used for DRAM, Flash, and SRAM module builds for the purpose of increasing depth or density.

Typically, TSOP packages are stacked up offering over 50% and 77% board space savings, when applied to dual and triple stacks, respectively.

At dual stack level, the height of the stacked devices allows for meeting the height guidelines of Jedec for DRAM modules.

As a result, no special mechanical restriction is placed on the system designers.

Chip-on-chip packaging does raise thermal issues, but a well-designed system with passive or active airflow always addresses this issue.

The technology is also susceptible to lead and package damage for stacking more than two devices, but factory testing should weed out any failures, and in any case the majority of devices are dual stack in nature where the problem is minimised.

On the plus side, benefits of chip-on-chip packaging include: the use of a single PLL, achieving very high component count support with minimum timing constraints at the module or board level; a standard design at the PCB level to mount a stacked chip; standard MFG/test procedures which means no special tooling is required; shorter signal traces, due to physical mounting of packages on top of each other where pins are making direct contact with each other rather than relying on a board trace to connect them to each other; and reduced manufacturing costs compared with having to mount monolithic memory cards to each other such as the card-on-card method used by some other vendors.

As a result of these tradeoffs, chip-on-chip stacking is the preferred method for using current memory technology to have access to tomorrow's memory densities.

In the area of chip-on-chip technology, Simpletech has been able to devise the most effective way of stacking using its patented IC Tower stacking technology.

The focus of IC Tower patented technology is to best optimise the implementation of the stacking at the component level.

Additionally, the approach can be used to build logic and memory stacks combination to address space constraints at hand.

IC Tower chip-on-chip stacking implementation addresses density and width stacking options for a dual-chip stack as follows.

To enable interchip connectivity, special PCB sideboards are used to make the connection form the bottom chip to the top chip.

The PCB sideboards use the vias to directly connect the common signal such as data pins between top and the bottom chips.

In the case of chip selects, the top chip pins are routed to an internal layer on the sideboard PCB and onto the unused pin on the bottom chip.

The rerouting to chip select pins is done to selectively turn the top and the bottom chips at different times, while allowing both stacked parts to share the same data pins.

Alternatively, one could make both the top and bottom chip have the same chip select and then route data signal pins of the top chips into the unused pins of the bottom chip and have a wider-databus device.

One of the benefits of the Simpletech stacking is the fact that it uses only standard surface mount equipment and no specialised equipment for its manufacturing process.

As a result, Simpletech can produce over 1 million stacked devices per month using only a single surface mount manufacturing line.

Simpletech patented IC Tower stacking is applied to build large quantity of stacked DRAM, Flash, and SRAM based stacked memory solutions.

Aside from DRAM implementations, typical Flash cards such as CompactFlash or ATA PC PCMCIA configuration gain a drastic benefit in offered density due to their standard yet limited board space.

As such, using chip-on-chip stacked Flash components can always offer a twofold density advantage (dual stack implementation for modules and cards compared with using monolithic Flash chips in the same footprint).

In the case of fast SRAMs, caching modules built based on stacked chip-on-chip SRAM can offer large memory caching in a limited space.

Applications driving the need for stacking are low-profile and highly dense rack-mount, blade and brick topology server implementation with single, dual and quad processor implementations, where small footprint is a must.

These computing engines are configured to be general purpose servers such as application, database servers or they can be self contained server/storage appliances such as web, load balancing, caching, streaming media, NAS, SAN, etc implementations.

As such, the multi-CPU configurations of these systems benefit from a DRAM density ratio that linearly scales for nonshared memory subsystems.

To truly benefit from high-clock-rate CPUs in server or embedded applications, designers can only realise the system performance benefits, when adding DRAM to these systems to allow for minimum access to the disk.

More information cached in larger density DRAM means less probability of having to go to disk to fetch the needed information.

DRAM access delays are in nanoseconds, while disk accesses are in microseconds.

This is where stacking of DRAM for multi-megabit/gigabit implementations allows easier time for engineers to have more room for other components in a predefined 1U or less footprint.

In the shared memory systems which are typically dual-processor configurations at the blade level, allowing for larger shared memory space, allows less context switching and trashing of data when two processors concurrently engage with the same pool of memory.

That translates into hundreds of CPU clock cycles saved when stacked memory can offer a giant memory pool as a resource to each of the CPUs in use.

Additionally the migration of x86 and RISC based solutions to 64 and 128bit data paths, and availability of operating systems that can support multi-gigabit memory subsystems means more memory is crammed in the same surface area.

Key operating systems such as Unix, Linux, and Window 2000/XP are maximising the capability of server's appliances and embedded designs to benefit from more stacked server DRAM in the system.

Given the exponential demand for the high-density and fast memory, Simpletech, is offering DDR-based low-profile DIMM, and SO-DIMM solutions using its IC Tower for peak density per memory socket.

Today's highest possible densities of SDRAM or DDR using 256Mbit chips are effectively stacked to achieve 512Mbit densities per single component footprint today, rather than waiting for 512Mbit monolithic chips to be readily available and be cost effective for use.

Additionally, given the increase in the clock rate of the DDR memories, setup and hold times for data access are being shaved.

Having parts stacked on top on each other reduces the trace length on the board for the same density by half, hence allowing easier time for system and board layout designers with the signal trace layout management on the boards.

This is achieved by eliminating the wire trace between two monolithic components, by allowing mounting chips on top of one another.

Another application that is benefiting from the stacking technology are networking and telecomms applications that need to fit highest possible DRAM density in the lowest possible surface area on embedded boards.

Specifically, to sustain high bandwidth throughputs at the control and data planes of the RISC processor and network processor based designs, respectively, designers opt to offer multiple channels of memory access using high-density stacked DDR SDRAM as their memory subsystem of choice.

Typical router or telecomms gateway DRAM usage is moving quickly from 128Mbyte towards 512Mbyte or even 1Gbyte per memory channel, and IC Tower stacking is the only way to achieve the higher density.

Other example of using stacking technology is in Flash storage area applied as a reliable storage device for commercial and industrial applications.

For example, Simpletech uses its chip-on-chip stacking technology to focus on offering the highest possible density on CompactFlash, ATA PC Cards, Flash disk modules and Flash drives.

In this case, MLC based AND Flash chips are dual stacked to achieve double the density for solid-state storage implementations using today's 1Gbyte Flash components.

This means Simpletech can produce: CompactFlash up to 1Gbyte; ATA PC Cards up to 4Gbyte cards, Flash disk modules up to 512Mbyte; and 2.5 and 3.5in form-factor Flash drives up to 8Gbyte.

The stacked Flash solutions address the growing demand for high density solid-state storage used by digital cameras and MP3 players as well as networking, telecommunication and factory automation markets served by Simpletech.

In the area of enhanced functionality versus maximisation of density, stacking technology can also be used to stack logic and memory components with one another.

For example, chip-on-chip stacking can be employed to save footprint area on handheld devices such as smart phones.

Specifically, stacks of linear Flash, EPROM, SRAM, and other logic can be stacked as long as the mechanical packaging of the individual ICs can overlap.

In summary, if highest possible memory density/functionality per surface area is the requirement of the system design, chip-on-chip IC-Tower stacking can make the solutions available through a viable cost model at present, rather than waiting for next generation memory components in the future.

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