Tool speeds timing signoff for nanometre ICs

Critic is a novel full-chip critical timing simulator designed for rapid post-layout analysis of cell-based digital ICs, including their associated clock networks.

Critic is a full-chip critical timing simulator from Nassda designed for rapid post-layout analysis of cell-based digital ICs, including their associated clock networks.

Critic complements traditional static timing analysis verification methods with fast, accurate analysis of timing performance of circuits targeted for nanometre process technologies at 130nm and below.

Nassda believes Critic is the first EDA tool able to automatically provide accurate analysis of nanometre effects on critical signal paths and clock networks for complex, high-performance digital ICs, comprising millions of gates and developed with customer-owned tooling (COT) flows.

The new tool fills the gap between conventional gate-level sign-off methods and the increasing requirements for more accurate post-layout timing analysis needed to ensure successful first silicon.

"Today, more and more design teams are using COT flows to take their designs from RTL-to-GDSII to get the best performance for their chips.

They claim that static timing analysis tools cannot deliver accurate numbers for designs in 130nm processes and for clock rates beyond 300MHz", said Simon Young, Product Line Director at Nassda.

"Built on our market leading HSIM simulation technology, we believe Critic provides the unique combination of speed, capacity and accuracy needed to determine the impact of nanometre effects on timing in critical path and clock nets for the full-chip.

With its transistor-level analysis, Critic allows designers to find and correct critical timing problems prior to manufacture rather than waiting for first silicon, to see if the design had any hidden timing flaws due to nanometre effects".

"nanometre effects in the digital realm mean that verification can no longer be limited to gate-level analysis", said An-Chang Deng, Nassda's President and Chief Operating Officer.

"Accordingly, Nassda is taking its leading transistor-level verification technology, and applying it to fill this much needed gap for accurate timing analysis in the cell-based digital IC realm".

Critic provides the detailed analysis needed to help ensure timing signoff.

Timing signoff is the point in the development of digital IC when timing performance of all of the signal paths meets the original design specification.

According to a recent study of chip design by CMP United Media, 79% of respondents identified timing as a very critical issue facing engineers when designing larger chips.

This result reflects the growing ineffectiveness of current methods to provide accurate timing numbers for nanometre circuits.

Currently design teams rely on static timing analysis to ensure that timing closure has been achieved.

Static timing analysis relies on the abstracted behaviour of individual gates or cells to perform its timing calculation.

With the latest nanometre silicon processes, however, the gate-level abstraction lacks the detail needed to resolve nanometre effects, which lie at the transistor level.

Furthermore, the use of static gate-level cell models neglects critical timing issues such as changes in cell delay due to different operating characteristics.

Transistor-level effects such as slew degradation, nonlinear loading, and coupling between adjacent interconnects can only be correctly analysed by a transistor-level simulation engine using interconnect parasitics for the critical paths and clock networks and dynamic values for voltages and currents rather than the ones and zeroes of traditional gate-level analysis.

Although transistor-level tools such as Spice and its fast-Spice variants have been around for years, these traditional tools lack the performance and capacity to deal with large post-layout designs comprising hundreds of thousand of critical nets with clock networks that can exceed 100,000 transistors all compounded by parasitic elements that can easily number in the millions.

In contrast, Critic provides the features needed to address growing challenges to accurate timing analysis in nanometre circuits.

Critic provides automatic transistor-level post-layout analysis of signal nets and clock nets with minimal designer intervention.

For analysis of the system clock, Critic identifies and traces the clock net automatically, back-annotates the clock net with interconnect RC parasitics, and sets control signals to sensitise the clock paths.

Critic then simulates the clock nets with the Spice model for each cell including precise fan-out loading.

Finally, it compares the clock pin delays with those reported by a static analysis tool.

Unlike conventional gate-level verification tools, Critic can handle any clock scheme including multiplexed clocks and domino logic because of its transistor-level approach.

Furthermore, rather than relying on limited gate-level cell models, Critic's use of Spice-level cell models helps ensure timing accuracy.

Generation of timing information in SDF permits Critic's high-precision timing results to be used for more accurate analysis of critical paths, or for optimisation of the design during physical implementation.

Critic also automatically analyses critical paths chosen by the chip designer, usually from a report generated by a static timing tool.

After the designer begins analysis, Critic automatically handles the subsequent steps, including back-annotation of post-layout parasitics, which can dramatically affect the timing of critical paths in nanometre designs.

Additionally, Critic can automatically include secondary loads to these paths to account for Miller capacitance and other loading effects.

After analysing the design, Critic automatically performs the tedious task of setting side branch values to enable or sensitise the critical paths as well as creating input patterns for dynamic simulation of the paths.

Unlike traditional solutions, which require a Spice simulation run for each path to be analysed, Critic simulates all paths together at once, reducing the number of simulation licenses required for analysis.

During this simulation, Critic uses the Spice model for each cell in each simulated path.

Finally, Critic compares the path delays with those reported by a static analysis tool and provides the designer with a detailed report on timing differences between those results and Critic's results.

Using these data, designers can fix timing problems and selectively optimise signal or clock nets for maximum performance.

Critic is available immediately directly from Nassda.

Pricing for time-based licenses start from $65,000.

Critic is supported on Sun Solaris, HP-UX, Windows XP/NT/2000 and Linux platforms.

(This was Electronicstalk's Top Story on 10 December 2002).

Back to top