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News Release from: Freescale Semiconductor | Subject: MPC8540
Edited by the Electronicstalk Editorial Team on 23 October 2001

Integrated host processor
aims for networking

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The MPC8540 is Motorola's first processor enabled with the high-speed RapidIO interconnect architecture

The MPC8540 is Motorola's first processor enabled with the high-speed RapidIO interconnect architecture, and is designed to deliver ultra high performance and integration to the networking and other embedded markets. Balancing processor performance, I/O system throughput and lower power consumption, the MPC8540 is a powerful control element for network routers and switches, storage subsystems, network appliances, and print and imaging devices.

"As the first RapidIO-enabled processor, and first processor to use the powerful e500 core, Motorola has reached two significant milestones with the MPC8540", stated Dr Larry Walker, vice president and general manager of Motorola's Networking and Computing Systems Group.

"Motorola is the market share leader in integrated circuits for communications systems, and we are committed to delivering leading edge solutions to the networking and embedded markets.

Designed to provide state-of-the-art performance and integration, the MPC8540 addresses the next generation needs of our customers, and provides Motorola with an ideal foundation for continued system-on-chip innovations".

The MPC8540 integrates dual gigabit Ethernet controllers, a 10/100 controller, a 64bit PCI-X controller operating at up to 133MHz, a DDR memory controller, a four-channel DMA engine, a multichannel interrupt controller and a DUART serial interface.

Designed as an SoC, the high level of integration enables simplified board design, low power consumption and an overall fast time to market solution for Motorola's customers.

The MPC8540 integrates 256Kbyte of on-chip L2 cache, a coherency module that connects the core and memory controller to processor peripherals, and introduces a revolutionary nonblocking crossbar switch fabric called OCeaN (on-chip network).

Leveraging the concepts of the RapidIO interconnect standard, OCeaN enables full duplex port connections at 128Gbit/s concurrent throughput and independent per port transaction queuing and flow control.

This innovative design permits high bandwidth, high performance, as well as the execution of multiple data transactions.

As with all processors implementing the PowerPC instruction set architecture, the MPC8540 is designed to be compatible with a rich set of operating systems, compilers, and development tools.

In addition, the MPC8540 will be manufactured using the advanced HiPerMOS 7 (HiP7) 0.13-micron copper fabrication process technology.

The performance range of the processor is projected to be 600MHz to 1GHz, with power consumption expected to be 6.5W at 800MHz.

Samples of the MPC8540 are expected to be available in the second half of 2002.

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