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Product category: Reference Designs
News Release from: Zarlink Semiconductor | Subject: ZLTE10565 reference design
Edited by the Electronicstalk Editorial Team on 11 July 2003

Reference design makes a PVR tuner in
seven chips

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Zarlink Semiconductor has unveiled a production-ready blueprint for a complete tuner subsystem used in a digital cable PVR.

Zarlink Semiconductor has unveiled a production-ready blueprint for a complete tuner subsystem used in a digital cable PVR Based on seven of Zarlink's proven RF (radio frequency) chips, the ZLTE10565 reference design is the first in a family of off-the-shelf designs that meets the growing need for higher-quality tuners in advanced digital TV products

PVRs, also known as digital video recorders, receive and store to hard drive two or more TV channels for "watch and record" and "pause and resume" viewing.

Like other digital TV products, PVRs require highly complex RF circuitry to reliably tune in coming channel signals.

To lower PVR costs and improve time to market, consumer electronics companies in Asia and other countries want "fit and forget" tuners that significantly reduce the need for time-consuming in-house RF design work.

With Zarlink's ZLE10565 reference design for a two-channel PVR tuner, manufacturers can quickly produce a compact cable PVR with reliable channel reception.

Several companies are currently evaluating the design.

"Customers want proven, cost-effective RF tuners that they can place on a motherboard or daughterboard and not have to worry about", said Jason Blake, Product Marketing Manager, Front-End RF Solutions, Zarlink Semiconductor.

"Our dual-channel digital cable PVR tuner design is a high-quality, easy-to-manufacture RF subsystem that meets their needs".

Zarlink's ZLE10565 reference design can be used in most commercial manufacturing processes with only minor changes.

The design integrates a front-end diplexer and dual-input splitter/amplifier with two double-conversion up/down tuners and full-stage IF (intermediate frequency) processing.

The design features seven high-performance Zarlink RF chips.

The low-noise SL2150D power splitter chip with built-in RF AGC (automatic gain control) handles the front-end splitter/amplifier function.

This chip requires no discrete input RF band splitting, which reduces RF complexity and eases manufacture.

The double-conversion up/down tuners each use the company's SL2101 broadband up-convertor and ZL10100 down-convertor.

Zarlink's SL2009 IF amplifier executes the final amplification stages.

The design also has a 5-30V convertor circuit for simple, 5V only operation.

Zarlink has implemented and fully tested the ZLE10565 reference design on a four-layer FR4 (flame retardant type 4) reference board with active circuitry measuring only 110 x 65 x 15mm.

The design features an innovative board layout that solves a major technical challenge associated with RF subsystems: oscillator "beat" frequency management.

Beat frequencies are cross-talk frequencies between oscillators in tuners.

Through optimal oscillator partitioning and metal shield placement, the design minimises crosstalk and coupling between tuners, and between the up/down convertor stages in each tuner.

Together with advanced software, these techniques eliminate oscillator beats in wanted channels, providing reliable reception over the full operating frequency range.

The ZLE10565 reference design supports an operating range of 50-860MHz and achieves differential and single-ended gain ratings of 81.5 dB and 76 dB, respectively.

The 44-MHz IF output drives most commercial QAM (quadrature amplitude modulation) demodulators.

The IF output is easily reconfigured to 36MHz, if required.

The design is fully compliant with CableLabs' DOCSIS (data over cable service interface specifications) and the OpenCable standard for digital cable channels.

It also meets DVB-C (Digital Video Broadcasting - Cable) and EuroDOCSIS requirements.

The ZLE10565 reference design is available now to qualified customers.

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