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Product category: Design and Development Software
News Release from: Mentor Graphics UK | Subject: Calibre xRC
Edited by the Electronicstalk Editorial Team on 30 August 2002

Transistor-level parasitic extraction for SoCs

Calibre xRC is a full-chip, transistor-level parasitic extraction tool that addresses the performance and accuracy requirements of today's most complex analogue mixed-signal SoC designs

Calibre xRC is a full-chip, transistor-level parasitic extraction tool that addresses the performance and accuracy requirements of today's most complex analogue mixed-signal (AMS) SoC designs. With Calibre xRC, Mentor has extended the core Calibre technology to address the distinct requirements of AMS SoC parasitic extraction.

Calibre xRC combines the proven performance, capacity and hierarchical geometry processing of the Calibre hierarchical engine with the accuracy and layout vs.

schematic (LVS) integration of xCalibre.

Traditionally, parasitic extraction tools are customised to handle the requirements of a specific design flow.

This specialisation forces SoC designers to either maintain multiple tools or use functionality that is unsuitable for a variety of design styles.

Unlike other tools, Calibre xRC was designed to deliver best-in-class extraction technology in a single tool for the full range of design styles found in AMS SoC designs (analogue, memory, full custom etc).

"AMS SoCs have created a whole new paradigm for parasitic extraction that necessitates mixed-level analysis", said Joe Sawicki, general manager, physical verification and analysis division, Mentor Graphics.

"Calibre xRC is the only product on the market that can accomplish that.

Using Calibre xRC within an SoC design flow ensures Mentor Graphics customers the most accurate and fastest verification and extraction performance available".

Today's AMS SoC designs can fail if the parasitic effects of passive interconnects are not properly addressed.

These effects are not only becoming significant for timing, but also for power, reliability, and noise.

Detailed analysis of these effects requires much more than a traditional extracted Spice netlist or timing file.

AMS SoCs require a comprehensive approach to parasitic extraction, including: accurate extraction algorithms to model interconnect effects on today's advanced processes; tight integration into the design environment to ensure efficient data handling for both upstream, design creation environments, and downstream post-layout analysis; and advanced data management to handle the enormous amount of parasitic elements that are extracted from current SoC designs.

While 3D field solvers are widely recognised as the most accurate method for analysing the parasitic behaviour of small test structures and critical nets, it is not feasible to apply this method to larger structures.

Calibre xRC employs a model-based engine to map the 3D characterised structure to real net segments for optimum performance.

Calibre xRC extracts accurate parasitics, including coupling capacitances, by taking all relevant geometries into consideration from substrate through top metal if necessary.

When Calibre xRC is used with Calibre LVST, it is the only production-proven AMS SoC verification tool that offers true mixed-level extraction.

Smaller-featured AMS SoCs require support for complex intentional device recognition and property extraction, support for accurate transistor-level extraction, and support for gate-level extraction for digital portions of the design.

The Calibre tools offer advanced intentional device recognition, intentional device property extraction and parasitic device extraction at both the gate and transistor levels to provide the highest level of accuracy for post-layout simulation.

Calibre xRC's tight integration with Calibre LVS enables back-annotation of simulation results to the source schematic.

In addition, Calibre xRC is part of the Calibre family of products, therefore Calibre DRC/LVS users can take full advantage of a single rule file and single tool flow for all verification and extraction tasks.

SoC designers are implementing a number of different circuit element types and have a variety of post-layout analysis requirements.

These analysis tools range from transistor-level, gate-level and hierarchical simulators that require parasitic data in various formats and with varying degrees of detail.

With other parasitic extraction tools, every analysis step requires a separate extraction to be performed.

Calibre xRC removes that bottleneck with a "one-run" incremental extraction technique.

All necessary data is extracted once, very quickly, and stored in a binary format.

Using the Calibre xRC formatter, designers can select between transistor-level, gate-level, hierarchical or select net results and sends data to different analysis tools (such as static timing or voltage drop analysis) with zero time invested in repeated extraction runs.

Calibre xRC is currently in beta evaluation with first customer ship planned for Q3, 2002.

Pricing starts at $140,000.

Calibre xRC runs on Solaris, HP and Linux.

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