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Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: SoC Encounter
Edited by the Electronicstalk Editorial Team on 6 December 2005

Design platform keeps
65nm processor on schedule

The Cadence Encounter digital IC design platform has helped PA Semi develop its new 65nm multicore PWRficient processor with a successful test-chip tapeout in March 2005

PA Semi's first PWRficient processor, a dual-core device operating at 2GHz with 5-13W power dissipation, is being developed from the ground up using the complete Encounter solution from RTL synthesis to GDSII. Silicon samples of the test chip are running at 2GHz. Based on the IBM Power Architecture, the scalable, power-efficient PWRficient platform-processor family targets the high-performance embedded and computing markets.

'The Cadence Encounter platform helped us achieve our test-chip tapeout and is assisting us in keeping our processor tapeout on schedule', said Sribalan Santhanam, Vice President of Engineering, Design Group, at PA Semi.

'The SoC Encounter XL RTL to GDSII system's advanced capabilities in RTL global synthesis, floorplanning, global physical synthesis and routing helps our designs to meet the required performance specifications, and the NanoRoute nanometre router's ability to support 65nm rules is unprecedented'.

'IBM Power Architecture has excellent momentum in many markets including computing, gaming and embedded applications'.

'Continued expansion into other markets requires active support from the design chain', said Tom Reeves, Vice President of Semiconductor Products at IBM Systems and Technology Group.

'We recognise this as a significant achievement by PA SEMI in developing its first Power Architecture based processor using the Cadence Encounter platform'.

To achieve the power, frequency, and density targets for the design, PA Semi tapped the strength of a complete SoC Encounter XL-based flow.

This RTL-to-GDSII system includes RTL global synthesis, prototyping, placement, optimisation, and routing.

Advanced capabilities in multi-objective low-power synthesis, global physical synthesis, clock-tree synthesis, manufacturing-aware extraction, and signal integrity and power analysis specifically address the complex issues of 65nm design.

'We are extremely happy to see PA Semi achieve its objectives using the SoC Encounter flow', said Wei-Jin Dai, Corporate Vice President, R and D for Cadence.

'The SoC Encounter system's strength is support for these types of complex, high-performance designs'.

'We are particularly proud to be a part of PA Semi's development of a 65nm product'.

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