Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: SoC Encounter
Edited by the Electronicstalk Editorial Team on 1 November 2004
Toshiba encounters first
time silicon success
Toshiba Corp and Toshiba Microelectronics Corp have successfully taped out a 24-million-gate chip using Cadence SoC Encounter
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The chip, with an end application in digital consumer electronics, is Toshiba's largest to date, and was designed using Toshiba's TC300 process for 90nm technology. As indicated by this successful tapeout, SoC Encounter is now fully supported as the digital IC implementation platform of choice for Toshiba's standard design environment.
Toshiba released the first version of this design environment in July to its worldwide internal design community and it is being used in several design projects already underway.
"Deploying Encounter's physical prototyping functionality in the early stage of the design process was critical to helping us avoid schedule delays for this design", said Takashi Yoshimori, Technology Executive SoC-Design of Toshiba's Semiconductor Company.
"We see this chip as one of the year's most important projects in the digital consumer arena".
Further reading
Digital IC platform sorts out 8-million-gate SoC
Toshiba America Electronic Components (TAEC) has successfully implemented an 8-million-gate SoC using the Cadence Encounter digital IC platform
Design platform enable DDR integration at 65nm
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform
"Our mission is to provide high quality designs with shorter turnaround time", said Kiyofumi Ochii, Senior Vice President of Toshiba Microelectronics Corp.
"SoC Encounter helped us meet our goal for this extremely challenging design by delivering speed, capacity and quality of results with a fully integrated design flow from prototyping through GDS".
To achieve the highest quality of silicon with the simplest design flow, Toshiba used Cadence SoC Encounter physical implementation technology and wires-first methodology.
SoC Encounter's powerful timing and signal integrity closure flow coupled with fast turn-around-time helped Toshiba achieve first silicon success for this scale of design.
"We are delighted to see Toshiba successfully implementing its largest 90nm design to date using SoC Encounter", said Wei-Jin Dai, Platform Vice President, Digital IC Implementation, Cadence Design Systems.
"Toshiba is one of Cadence's most highly valued customers and this tapeout underscores our ongoing commitment to customer success as measured in quality silicon".
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