Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Allegro
Edited by the Electronicstalk Editorial Team on 26 July 2005
PCB design software
is made for teamwork
The latest Allegro technology shortens design cycle time by enabling team-based PCB system design throughout the design flow
Cadence Design Systems has released a new version of its Allegro system interconnect design platform. Allegro now further shortens design time and strengthens the IC design chain with enhancements from design entry to printed circuit board (PCB) design. The latest Allegro technology shortens design cycle time by enabling team-based PCB system design throughout the design flow.
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The entire breadth of the Allegro product line has been enhanced with greater productivity and ease-of-use capabilities.
It further strengthens the design chain by helping IC companies distribute Spectre transistor-level models so that their customers can design-in complex ICs faster.
The release includes new technology for multiple-style design creation, real-time design for assembly (DFA) driven placement and an improved constraint-driven design flow.
'We are especially pleased with Allegro's new real-time DFA driven placement capability', said Charlie Davies, ECAE Application Engineer of Harris Government Communication Systems Division.
'This feature guides component placement, allowing us to create manufacturable designs appreciably faster'.
Further reading
Interconnect design platform enhanced
Cadence Design Systems has revealed the latest advances in its IC packaging technology, slated to improve productivity and accuracy for shorter design cycle time
Design platform aids chipset implementation
The Cadence Allegro system interconnect design platform has been further customised for engineers designing printed circuit boards (PCBs) for advanced chipsets
Design platform enable DDR integration at 65nm
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform
'This capability further enhances Cadence's constraint driven PCB design flow'.
Allegro now includes Allegro Design Editor, the industry's first PCB multiple-style design creation environment.
Allegro Design Editor helps make design creation up to 10 times faster with a spreadsheet-like interface, schematics and Verilog-language-sensitive editor customised for PCB design.
This new design creation paradigm for capturing PCB and multicomponent package designs provides a connectivity-based solution introducing an easy-to-learn, easy-to-use environment that supports multiple styles for creating design intent.
'With a new design entry paradigm leveraging a core constraint management system all the way to the back end of the design process, the latest advances in the Cadence Allegro platform provide us with a design flow tailored to our needs', said Tim Kent, Vice President of Engineering at high performance computing system vendor Liquid Computing.
'Some of our designs are highly constrained with large pin-count devices'.
'With Allegro Design Editor, we believe Cadence is uniquely positioned to help customers like us dramatically accelerate design creation for these complex PCB designs'.
'We also plan to adopt the new Allegro design partitioning technology in the near future'.
'This latest enhancement to our SPB product line means our customers have a real-time approach to design for assembly and the technology advancements they need to address their most pressing challenges in the constraint-driven PCB design flow', said Charlie Giorgetti, Corporate Vice President and General Manager of System Design at Cadence.
'This latest release of Allegro is another example of how Cadence continues to lead the way in the silicon-package-board co-design market'.
Available now, the latest Allegro release accelerates design creation time by improving design reuse with schematics on front-end constraints stored with each schematic block.
Real-time DFA Design Rule Checker (DRC) guides the placement of components for faster design.
A component revision manager in design entry HDL automatically verifies that schematic symbols are up to date to prevent the use of outdated parts previously not discovered until later in the design cycle.
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