Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Allegro
Edited by the Electronicstalk Editorial Team on 23 August 2005
Interconnect design platform enhanced
Cadence Design Systems has revealed the latest advances in its IC packaging technology, slated to improve productivity and accuracy for shorter design cycle time
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The Cadence Allegro system interconnect design platform has been enhanced with improvements in the Cadence constraint-driven IC packaging codesign flow and enhanced power and signal integrity (SI) analysis accuracy. As IC packaging technology continues to change rapidly, its importance as a critical link in the silicon-package-board design flow grows.
This precipitates the need for strong capabilities to address current and future packaging technologies such as wirebond, perimeter array flip-chip, full array flip-chip, and stacked multi-die packages.
'These latest advances in Cadence IC packaging technology provide Amkor and our design customers with significant opportunities for savings in design cycle time while maintaining and improving overall quality', said Steven Lowder, Amkor's Vice President of Worldwide Design.
'As a leading provider of packaging and test solutions for complex multi-die designs, Amkor and our customers benefit from the Cadence commitment to enabling IC package co-design and analysis'.
This new Cadence IC packaging technology, part of the latest Allegro release, improves accuracy for advanced package modelling with an easy-to-use, unified design flow for faster creation of complex package models.
With the Cadence IC packaging solution, complex packages are modelled by solving for 3D structures and generating multiport S-parameter models that are accurate up to 4GHz.
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The Cadence Allegro system interconnect design platform has been further customised for engineers designing printed circuit boards (PCBs) for advanced chipsets
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Faraday Technology Corp uses Encounter Conformal Constraint Designer technology to validate customers' design constraints, ensuring the quality of the design before implementation
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This embedded 3D field solver approach also provides faster model creation compared with the traditional approach of loosely integrated point tools.
'These latest advances in Cadence IC packaging technology provides us with impressive savings in design time', said Kevin Roselle, CTO of Bayside Design.
'As we move into the next era of packaging, this kind of support from our design automation software partners is extremely important, especially in the area of power delivery design and analysis'.
As part of the latest TSMC Reference Flow 6.0, the Allegro Package Designer provides an integrated power integrity verification flow with VoltageStorm Dynamic Gate power analysis so that IC core dynamic IR drop in the chip can be predicted, including package load effects.
Integration creates models of the package PWR/GND structures, which map directly to the IC bump ports and create a complete package-silicon PWR/GND network for verification.
The Allegro-VoltageStorm integration automates the flow, eliminating error-prone manual model generation and mapping.
'Dynamic IR drop is a major concern for both chip and package design', said Edward Wan, Senior Director of Design Service Marketing at TSMC.
'Without package IR loading, high-speed digital designers may have incomplete dynamic IR drop margins that severely reduce chip performance'.
'Reference Flow 6.0 incorporates the Allegro Package Designer's integrated flow that helps designers simultaneously evaluate these effects in an automated and efficient manner'.
'These additions to our production proven IC packaging technology extend our leadership in this important market', said Jamie Metcalfe, Vice President of Marketing for IC Packaging Codesign Products at Cadence.
'We continue to focus our technological development on simplifying the design process and helping manufacturers design products for fast volume production'.
Productivity and ease-of-use improvements include wirebond design reuse, which provides the ability to reuse complex wirebond tiers in different designs.
The addition of a Microsoft Excel interface for I/O planning data completes the offering.
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