Product category: Intellectual Property Cores
News Release from: Cadence Design Systems | Subject: PEX Endpoint Controller IP
Edited by the Electronicstalk Editorial Team on 26 April 2005
Endpoint controller certified
for PCI Express
Cadence Design Systems' PEX Endpoint Controller IP, integrated with Rambus' PCI Express PHY IP, has passed PCI-SIG compliance testing and been added to the PCI-SIG Integrators List
Cadence has taken a vertical approach to meeting the needs of PCI Express customers, combining technologies from industry leaders to enable customers to reduce risk and increase productivity. In addition to design and verification IP, the vertical approach combines emulation, board design and protocol analysis tools targeted at the PCI Express architecture.
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In preparing for the compliance workshop, where devices need to pass compliance and interoperability testing, verification IP from Denali and PCI Express analysers from Catalyst helped Cadence develop a higher-quality product.
Chuck Trefts of Catalyst, a veteran of many PCI-SIG Compliance Workshops, said: 'The performance of the Cadence/Rambus test board against our PCI Express compliance test suite was excellent, among the best PCI Express solutions I have seen'.
'The PCI-SIG is pleased to see Cadence's support for the PCI Express architecture', said Al Yanes, PCI-SIG President.
'Cadence's addition to the Integrators List underlines the value of our approach to empower member companies and shorten the design cycle of innovative products based on the PCI Express technology'.
Passing compliance testing is a significant milestone for the serial link portfolio agreement announced in July 2004 between Cadence and Rambus.
Further reading
Software takes holistic view of PCB design
System interconnect design platform adds new capabilities at all stages of printed-circuit board design
Single simulator covers all IC technologies
End-to-end simulation and verification software for custom IC uses a common database of netlists and models to simulate analogue, RF, memory and mixed-signal designs
Kit cuts the cost of low-power IC design
Design kit enables engineers of different experience levels to adopt advanced low-power techniques with minimal risk and deployment effort
In March, Cadence and Rambus announced that Open-Silicon, a fabless ASIC company, licensed multiple Rambus Raser serial link offerings through the Cadence-Rambus reseller programme.
The PCI Express technology has become established as the leading high-speed serial interconnect.
However, its complex digital protocol layers and multigigahertz analogue interfaces make design and verification more complex.
'Working with Cadence, we are able to offer high-speed I/O, an unmatched portfolio of off-the-shelf IP backed up with integration and customisation services', said Jean-Marc Patenaude, Director of Marketing, Rambus.
'Success in testing at the compliance workshop is further evidence of our ability to provide complete, proven interface solutions'.
Dirk Wieberneit, Vice President and General Manager of Product Development Consumer of Micronas, which successfully passed PCI-SIG compliance with its nGene product line, commented: 'The familiarity of Cadence Engineering Service's teams with both PCI Express technology and verification tools from vertical solution members Denali and Catalyst, as well as the excellent cooperation between Cadence and Micronas in verifying the Cadence IP under real application conditions, including the software, were the key success factors in reaching compliance and interoperability'.
Micronas' nGene is the world's first dual-channel multimedia controller integrating PCI Express for the PC-TV market.
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