Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial Team on 25 February 2005
S3 encounters multiple designs at 90nm
The Cadence Encounter digital IC design platform has helped Silicon and Software Systems deliver multiple 90nm designs over the past 18 months
The Cadence Encounter digital IC design platform has helped Silicon and Software Systems (S3), a leading System IC design company, deliver multiple 90 nanometre designs over the past 18 months. The designs have ranged in complexity and size from 1 million to 4 million gates, with performances in excess of 600MHz.
This article was originally published on Electronicstalk on 25 February 2005 at 8.00am (UK)
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'S3 has made a substantial investment in developing flows and expertise to minimise the risks for our customers in 90-nanometre system IC design, with a focus on performance and high quality of results', said Dermot Barry, General Manager of the System IC Business Unit at S3.
'The SoC Encounter digital IC design tool provides the early feasibility testing and budgeting we require for our complex designs, and a rapid timing and SI (signal integrity) closure with the CeltIC and NanoRoute'.
S3's successful 90 nanometre results are on par with more mature process technologies.
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With 15 designs started at 90nm to date, and two 65nm designs underway, S3 is at the leading edge of system IC design in an industry now seeing volume ramp-up at the 90nm technology node.
Recent S3 deliveries include a 4-million-gate system on a chip in a nine-metal-layer, 90nm process with clock speeds in excess of 600MHz, and a 1-million-gate 90nm CMOS ARM11 subsystem with multiple power domains.
'S3 has clearly demonstrated leadership at the 90-nanometre technology node, and is further extending its leadership with multiple, complex 65-nanometre designs currently underway', said Wei-Jin Dai, Platform Vice President, Digital IC Implementation at Cadence.
'We applaud the engineering team at S3 on its success and are proud that it has chosen Encounter as the standard for leading-edge implementation'.
'Once again, Encounter is recognised as essential technology by an important customer'.
The Encounter platform covers the spectrum of nanometre design technology from prototyping and partitioning to final timing and SI closure on the most complex designs.
Encounter's partitioning and prototyping methodology allows designers to quickly achieve optimal timing budgets and floorplanning in the early phases of the project.
Its crosstalk prevention features, coupled with NanoRoute SI aware routing provide a fast path to GDSII and final design closure at 90nm.
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