Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial Team on 9 September 2004
Reference flow looks beyond 130nm
A new digital reference flow from Cadence Design Systems and UMC targets SoC designs at 130nm and below
The reference flow uses IP libraries and memories from Faraday Technology Corp, a global provider of silicon-proven IP and ASIC design services. This RTL-to-GDSII reference flow takes advantage of UMC's leading-edge technology that allows both high-speed and low-leakage transistors to be combined onto a single chip-ideal for wired and wireless applications.
This article was originally published on Electronicstalk on 9 September 2004 at 8.00am (UK)
Related stories
Design platform enable DDR integration at 65nm
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform
Design software cuts 65nm TV chip time to market
STMicroelectronics has used the Encounter digital IC design platform and system-in-package design technology on its industry-first 65nm dual HD decoder
Based on the Cadence Encounter digital IC design platform, the reference flow is being validated in silicon using UMC's 130nm logic (CMOS) high-speed process.
With increasing interdependencies between design and manufacturing at 130nm and below, this integrated reference flow allows customers a predictable path from RTL to silicon and can help reduce the need for iterations in the design phase and decrease mask respins while maintaining the quality of silicon (QoS).
This is especially critical when designing multi-million-gate SoCs and can provide a clear time-to-market advantage.
"UMC continues to strengthen its portfolio of SoC foundry solutions to help designers of complex system-on-chips more quickly realize silicon success", said Ken Liou, Director of UMC's Design Support Division.
"By working closely with Cadence, we can ensure that the performance and capabilities of their digital IC solutions works smoothly with our process flow".
Further reading
Design flow overcomes lithographic limitations
Cadence Design Systems has created a lithography-aware design flow and has defined an interface that will link resolution enhancement technologies with physical design and verification
Platform enables early array signoff
Toshiba Corporation and Toshiba Microelectronics Corporation have successfully taped out the first UniversalArray chip with Cadence Encounter digital IC implementation
Design platform eases migration from 90 to 65nm
The Cadence Encounter digital IC design platform has helped Silicon and Software Systems (S3) to successfully tape out a new production 65-nanometre design
This reference flow incorporates leading Cadence technologies, including Encounter RTL Compiler, First Encounter GPS (Global Physical Synthesis), NanoRoute, Fire and Ice QX, CeltIC-NDC, VoltageStorm power analysis and Assura physical verification tools.
It uses a "wires first" methodology to address key nanometre design issues, such as timing closure, signal integrity and power integrity.
"We are very pleased that the Faraday library and memories have been successfully integrated into the UMC and Cadence reference flow", said Hsin Wang, Associate Vice President of R and D at Faraday.
"Our libraries have been optimised through all aspects of the flow to support floorplans, physical synthesis, legal placements, clock tree synthesis and power routing for digital designs".
"In addition, our library and memory views have been enhanced to enable power and signal integrity checks as part of the flow".
"No one company alone can address today's nanometre design challenges and industry disaggregation", said Jan Willis, Senior Vice President of Industry Marketing, Cadence.
"Collaboration is essential for customer success".
"This digital reference flow is another milestone in our ongoing collaboration with UMC to enable customers to meet their time-to-market goals predictably".
The UMC and Cadence digital reference flow kit is currently available at no charge to UMC customers, from UMC sales representatives or accessible online through MyUMC.
On 5th October 2004, UMC and Cadence will hold a free web seminar on how to enhance design team productivity and silicon reliability with the UMC and Cadence Reference Flow.
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• NEW
• Electronicstalk Home Page
Related Business News
Icoa Is Partnering With Anchorfree To...
...Enhance And Monetize Thousands Of Wi-fi Hotspots. Icoa, Inc., a national provider of wireless broadband Internet access and managed network services in high-traffic public locations, and AnchorFree Inc., a rapidly growing Wi-Fi community powered by advertising, have announced today that they are partne
South Africa: Lyons to Build Hi-Tech...
...Office Park in Belarus. Lyons Financial Solutions, a South African property investor, and other companies have won a R4bn contract to build an office park for software and scientific businesses in Belarus.
Agilent to buy private defense firm NetworkFab
Olympics raises demand for IT contractors
The number of IT contractors working in the engineering sector has almost doubled in 12 months because of demand generated by the 2012 Olympics, according to contractor Giant Group PLC.
Stellar Appoints CIO to Lead Call...
...Centre Outsourcing Technology Strategy. Stellar, a leading global business process outsourcing provider, today announced that Warwick Marx has been appointed Chief Information Officer of Stellar Asia Pacific.
Search the Pro-Talk network of sites
