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Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Virtuoso
Edited by the Electronicstalk Editorial Team on 18 September 2003

Design platform maintains nanometre-scale accuracy

The Virtuoso custom design platform is claimed to be the world's first comprehensive platform for fast, silicon-accurate custom, analogue, RF and mixed-signal design

The Virtuoso platform boasts the industry's only specification-driven environment, the first multimode simulation using common models and equations, up to 10x faster accelerated layout, advanced silicon analysis for 130nm and below, and a full-chip, mixed-signal integration environment. The Virtuoso platform is available on both the industry-standard OpenAccess database and the popular Cadence CDBA database.

With the Virtuoso platform, design teams can quickly design silicon that is right and on time at process geometries from 1um down to 90nm and beyond.

With this platform, Cadence is upgrading all its existing custom technologies and shipping several new products.

The new Virtuoso multimode simulation provides Spice, FastSpice, AMS and RF capabilities - all using common syntax, models and equations.

Virtuoso LE Turbo adds design-rule driven, QuickCell parameterised cell specification, and wire-to-wire editing capabilities to Virtuoso LE.

The platform also adds Virtuoso AMS Silicon Analysis for 130nm and smaller circuits, and Virtuoso HF-AMS silicon analysis, which includes additional capabilities for 1GHz+ circuits.

"Predictability and productivity are critical for today's advanced custom designs", said Lavi Lev, Cadence Executive Vice President and General Manager.

"They require the speed of top-down design combined with the silicon accuracy of bottom-up design-all in a comprehensive environment.

That's something only the Virtuoso platform delivers".

Custom digital, analogue, RF, and mixed-signal design becomes exponentially more complex and faces exponentially more physical effects as companies move to more aggressive process technologies.

These demands have become extremely acute as companies integrate high-performance custom circuitry with massive digital designs at 130nm and beyond.

Until now, the electronics design industry's core custom design tools and environments have not kept pace.

The Virtuoso platform significantly raises the bar, providing extensible, new-generation capabilities which enable a fast, silicon-accurate design methodology.

Importantly, the platform preserves existing investments in current Cadence custom technologies and environments as design teams migrate to the OpenAccess database.

"The Cadence Virtuoso custom design platform will be the backbone of our next-generation mixed-signal flow", said Jean Pierre Geronimi, CAD Director of Central R and D Design Automation at STMicroelectronics.

"Our decision was mainly driven by the productivity gain we have seen both in the point tools and the new OpenAccess database infrastructure.

More specifically: for tools, we have much appreciated the enhancements to Virtuoso, CCAR power routing and preview, particularly in the area of 130 and 90nm support, where we contributed with our process specifications, while, in the OpenAccess space, we were very pleased with the capacity and performance seen in the new OA-native Virtuoso Chip Editor for managing the final chip finishing phase of the physical design".

With the Virtuoso platform, Cadence is the only company to offer Spice, FastSpice, AMS and RF simulation as both best-of-breed stand-alone simulators and in a single multimode simulation licensing model - Virtuoso Multimode Simulation - which allows users to select the simulation type at runtime.

All Virtuoso simulators use common syntax, models, and equations ensuring identical results at the highest accuracy settings.

Moreover, these are the same models and equations generated by the Virtuoso advanced device modelling tools.

This powerful combination supports fast full-chip top-down simulation, silicon-accurate bottom-up simulation, and everything in between.

Other enhancements include 3x faster Spice performance and full HSpice compatibility.

"A fast, silicon-accurate design platform is critical to successful mixed-signal and RF designs, especially on advanced process technologies", said Ed Chen, Director of Services Product Marketing at TSMC.

"Today, the Virtuoso platform supports TSMC's 90nm process requirements and models.

Our broad alliance with Cadence is differentiated by a joint focus on silicon-accuracy ranging from the characterisation and simulation of the latest generation of models through the codevelopment of TSMC process design kits (PDKs) that support the Virtuoso platform".

In the Virtuoso platform, Cadence has boosted performance in its accelerated layout tools by over 10x, cutting complex operations from minutes to seconds and making most operations nearly instantaneous.

Design-rule driven support ensures correct-by-construction layout, which is especially important 130nm and below.

Additional enhancements include OpenAccess support for up to 3x capacity and rectilinear floorplanning within Virtuoso XL.

The recently announced Virtuoso Chip Editor provides fast, full-chip integration for custom, cell-based, and mixed-implementation designs.

"National has been very successful using the Virtuoso accelerated layout in our analogue and mixed-signal designs", said Bill Meier, Senior CAD Manager at National Semiconductor's Technology Infrastructure Group.

"Its connectivity-driven capability is key to fast correct-by-construction layout, and the platform's ability to easily run parasitic resimulation in the Virtuoso platform is a real plus".

For analogue/mixed-signal design at 0.18um and below, high-accuracy parasitic extraction, analogue IR-drop analysis, and power-grid electromigration analysis become critical for circuit design and full-chip electrical verification.

The new Virtuoso AMS Silicon Analysis product combines all of these capabilities with design rule checking (DRC) and layout-versus-schematic checking (LVS).

The new Virtuoso HF-AMS Silicon Analysis adds inductance extraction, electromigration, and a field solver for high-frequency (1GHz+) analogue/mixed-signal designs.

These capabilities enable design teams to quickly perform silicon-accurate analysis that can save extremely expensive unplanned-respins.

Virtuoso full-chip integration takes advantage of the industry-standard OpenAccess database to eliminate the massive file transfers otherwise needed for SoC chip finishing and ECO flows.

OpenAccess also enables seamless, bidirectional data exchange between the Cadence Virtuoso and Cadence Encounter platforms for improved productivity.

In addition, the company is delivering the Virtuoso Analogue/Mixed-Signal Baseline Flow based on the ACD methodology.

This detailed, step-by-step flow is based on a distributable reference design and PDK.

It is immediately available via demonstrations, hands-on workshops, documentation, training, and methodology services.

Cadence plans to deliver additional baseline flows over the next year.

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