Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: PCB and IC packaging design environment
Edited by the Electronicstalk Editorial Team on 21 July 2003
Full solution for
gigabit-speed PCB systems design
Release 15.0 of the Cadence PCB and IC packaging design environment includes enhancements and innovations spanning the entire integrated flow
Now, for the first time, engineers have a complete environment for designing and implementing gigabit serial interfaces in high-speed PCB systems through a simulation and constraint-driven differential interconnect implementation from die-to-die across all three system fabrics: silicon, IC package, and PCB.
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This robust capability puts first-time design success within reach of computer and network companies.
Other productivity-enhancing advances include: a new capability for the automated design of stacked-die systems-in-packages (SiP); unified and automated library part creation, validation and management, environment; dynamic real-time copper pour, plough and editing; and advanced simulation capabilities for signal integrity model verification.
"The gigabit interconnect technology that allows systems designers to meet market demand for more system bandwidth is causing a revolution in design at the board and IC package levels", said Charlie Giorgetti, Corporate Vice President and General Manager of the Cadence PCB Systems Division.
"Engineers are facing unprecedented signal integrity, timing and routing issues, compelling them to look across design domains and consider the high-speed interconnect from I/O cell-to-I/O cell across IC packages and PCBs".
Key to successful gigabit serial interface design is the creation, constraint, simulation and management of differential signals throughout the entire design flow.
Further reading
Software takes holistic view of PCB design
System interconnect design platform adds new capabilities at all stages of printed-circuit board design
Single simulator covers all IC technologies
End-to-end simulation and verification software for custom IC uses a common database of netlists and models to simulate analogue, RF, memory and mixed-signal designs
Kit cuts the cost of low-power IC design
Design kit enables engineers of different experience levels to adopt advanced low-power techniques with minimal risk and deployment effort
Features in the Allegro layout and SpecctraQuest signal design and analysis environments enable designers and engineers to reduce design cycles by introducing the ability to design a comprehensive set of rules within a constraint management system and then use those rules to drive layout and routing.
This can eliminate numerous iterations and enables first time design success.
As progressively more manufacturers turn to system-in-package (SiP) technology to reduce product footprint, integrate disparate technologies and reduce time to market, designing integral die stacks becomes increasingly attractive.
A new multiple stacked-die design and editing environment and an automatic wirebond creation capability in the Cadence Advanced Package Designer speed the design process, helping manufacturers get products to volume production quickly.
"SiP technology offers incredible performance and cost advantages for manufacturers.
Designers, however, face enormous challenges in creating the requisite complex stacked-die structures", said Bret Zahn, Vice President of Worldwide Design and Characterisation, ChipPAC.
"As the market leader in stacked-die package design, assembly, and test, ChipPAC uses the new Cadence capability to deliver the highest-performance and most cost-effective packaging solutions to our customers".
New capabilities in PCB Librarian Expert 15.0 address process bottlenecks created as librarians manually struggle to enter, create and validate component data for the large-pin-count devices common in today's designs.
The new release advances electrical component library development and management through: use of XML for data-driven symbol generation, management and portability; the capability to import pin and package data directly from internet-available datasheets in PDF or CSV formats; online part validation to user-definable company standards, ensuring that parts comply 100% with specification; and automatic library management routines that track changes between part versions, providing detailed reporting of revision differences.
Outer-layer ground planes are pervasive in today's complex, high-speed PCB designs, commonly used for shielding, noise reduction and supplying selective power to sensitive subcircuits.
Today, creating and modifying such entities can be very time-consuming due to complex manufacturability requirements.
Addressing this in Allegro 15.0 is a fast, easy-to-use solution for real-time copper pour that allows for dynamic ploughing and healing during interactive or automatic routing.
Importantly, the new feature allows shapes to be edited at any time - without any need for recreation or postprocessing - making ECO changes easy.
A new Spice-to-Ibis Model Integrity module in the SpecctraQuest SI Expert solution helps users create Ibis models from Spice models quickly.
With the output of the Spice simulation run, Ibis and buffer options file, users can now create known good Ibis models quickly.
Model Integrity identifies I/V and V/t tables for typical, maximum and minimum corner cases from the Spice run file.
As the number of points in a Spice simulation run could be far greater than the maximum number of points allowed in Ibis, the Model Integrity Spice-to-Ibis module applies an intelligent and proven best curve fitting algorithm to provide accurate Ibis models.
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