DSP-based transceivers drive faster over copper

A novel line of high-speed physical-layer transceivers uses DSP techniques to eliminate signal integrity problems associated with 5 and 10Gbit/s data transmission over backplanes and copper media.

A novel line of high-speed physical-layer transceivers uses DSP techniques to eliminate the signal integrity ("noise") problems associated with 5 and 10Gbit/s data transmission over backplanes and copper media.

The D-PHY family of serdes ICs is based on a new architecture that combines Analogix's WideEye technology - a set of adaptive DSP-based noise-cancellation techniques - with advanced analogue signal conditioning.

Unlike analogue-only solutions, which simply mask detrimental signal effects such as crosstalk and reflections, the D-PHY family actually removes these effects, ensuring maximum signal integrity.

With noise problems eliminated over standard FR-4 backplanes and very-short-reach (VSR) system-to-system copper interconnects, system designers can: upgrade existing backplane systems with four-fold performance; design new, higher-speed systems with low-cost connectors and easily manufactured FR-4 materials rather than far more complex and expensive materials; or replace fibre-optic intersystem connections with much lower-cost standard unshielded twisted pair (UTP) or InfiniBand copper cable at distances up to 50m.

The D-PHY family is designed for use in enterprise switches and routers, carrier-class transport equipment (including optical switches and cross-connects), Fibre Channel and IP- based storage systems, and high-end servers.

The first D-PHY products, D-PHY 5Gbit/s backplane transceivers, are being released now.

A 10Gbit/s serial backplane transceiver family and a 10Gbit/s serial interconnect over copper IC family will be introduced later this year.

Ted Rado, Vice President of Marketing at Analogix, said: "The ubiquitous copper-based FR-4 backplanes in today's systems were designed when speeds of 5Gbit/s and above weren't even imagined".

"Now designers of switches, servers, storage arrays and the like want more performance, but they want to get it by upgrading, not replacing, their existing systems".

"As vendors try to design new high-speed cards that fit into old FR-4 backplanes and interoperate with existing cards, they face major noise issues that analogue techniques can't handle - not just signal attenuation but crosstalk and reflections".

"Since the backplane itself has a fixed number of traces, the burden is on the silicon to deal with the increased noise while pushing more performance through those traces".

"The same issues surface in system-to-system interconnect, where, even at distances of under 50 metres, copper media have severe noise issues at speeds over 1Gbit/s", Rado added.

"Thus far, expensive, power-hungry fibre solutions have been the only choice".

Analogix's solution is the D-PHY architecture, an advanced analogue/DSP-based approach that maximises signal-conditioning flexibility.

Like traditional analogue-based serdes technology at 3.125Gbit/s and below, D-PHY devices offer standard transmitter-programmable pre-emphasis and swing control.

Up to now, companies targeting speeds beyond 3.125Gbit/s have incorporated more advanced analogue receive-based equalisation, typically in the form of decision feedback equalisers (DFEs).

The D-PHY architecture's two chief elements - one analogue, one DSP - offer significant advantages over such approaches.

These include the multistage continuous-time linear equaliser, an advanced analogue signal-conditioning element that has the benefits of DFE-based solutions with half the power consumption and die area.

It also scales more effectively to 10Gbit/s because its feedback loop does not occur at the maximum frequency.

Also crucial is the company's WideEye technology.

A set of DSP-based adaptive signal- conditioning elements, WideEye includes adaptive equalisation, adaptive reflection and crosstalk cancellation, and error correction coding.

These techniques, unprecedented in backplane devices, maximise system vendors' design margins and flexibility in both upgraded and new designs.

To address power concerns implicit in DSP technology, D-PHY chips offer a unique PowerSelect option, which lets users turn off individual WideEye functions for high-quality channels; this brings typical power consumption down to 2.9W or less.

The D-PHY 5G backplane transceivers offer 1.25 to 6.25Gbit/s serial transmission across up to 60in of standard FR-4 backplane material and two connectors.

Two versions are available.

The D-PHY 4x5G quad transceiver, with four high- speed links, provides up to 25Gbit/s full-duplex transmission.

The D-PHY 2x5G dual transceiver, with two links, performs at up to 12.5Gbit/s.

NRZ binary encoding on both devices ensures backward-compatibility with lower-speed serdes transceivers.

All D-PHY devices are compliant with the Optical Internetworking Forum's Common Electrical I/O (CEI) 6G+ specification.

Each D-PHY device also has eight low-speed (800Mbit/s to 3.125Gbit/s) serdes links.

Flexibility is increased by three multiplexing options: 1:1, 2:1 and 4:1; a unique legacy mode available with 1:1 multiplexing detects connection with another serdes device (such as an XAUI transceiver), allowing new cards to interoperate with existing ones.

Comprehensive built-in self-test (BIST) functionality includes on-chip PRBS generators and error checkers as well as low- and high-speed loop-back paths for independent testing of all chip elements.

D-PHY devices also offer real-time bit error rate (BER) monitoring capabilities by polling MDIO- or I2C-controlled WideEye DSP registers.

The D-PHY 5G backplane transceiver is sampling now and will be available in production volumes in June.

High-volume prices are $49 each for D-PHY 4x5G devices and $28 each for D-PHY 2x5G devices.

The devices come in JEDEC-standard 260-pin HSBGA (heat slug ball grid array) packages.

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