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Design and Development Software
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Software automates PID controller development
A new EDA tool fully automates the development of analogue "proportional, integral, derivative" control loops
News from Anadigm (9 June 2003)
Online design tools gain power support
National Semiconductor reckons its Solutions.National.com design website and Webench 4.0 toolset comprise the industry's most comprehensive suite of free design tools
News from National Semiconductor (6 June 2003)
Honeywell signs up for embedded code generation
Honeywell ES and S is to deploy embedded code generation technology based on Matlab and Simulink to develop increasingly complex airborne software and systems
News from The MathWorks (6 June 2003)
Timing analyser speeds to faster signoff
Incentia Design Systems has improved the performance of its TimeCraft full-chip gate-level static timing analyser for multi-million-gate high-performance designs
News from Incentia Design Systems (6 June 2003)
Development system comes with captive processor
Developers of smart handheld devices now receive Motorola's high-performance low-power applications processor as part of Metrowerks' advanced CodeWarrior Development System for i.MXL
News from Metrowerks Europe (6 June 2003)
Infineon sorts out nanometre designs
Infineon Technologies has adopted the Mentor Calibre design-to-silicon platform, and the embedded deterministic test product, TestKompress, as key enablers for its nanometre IC design strategy
News from Mentor Graphics UK (5 June 2003)
Virtual prototyper boosts design productivity
The Calypso silicon virtual prototyping (SVP) system is built on a foundation of patented Monterey Progressive Refinement technology
News from Monterey Design Systems (5 June 2003)
Programme takes physical IC design to new level
The Monterey Calypso Vanguard programme aims to address the rising cost of designing multi-million-gate chips and the severe penalties of making uninformed decisions early in the design cycle
News from Monterey Design Systems (5 June 2003)
FPGA software simplifies migration
Version 9.5 of QuickWorks development software provides enhanced support for the entire Eclipse-II family of field programmable gate arrays
News from QuickLogic (4 June 2003)
Pair to link design tools with verification
CoWare and Verisity have agreed an integration roadmap for their products, which will connect new, breakthrough SystemC system-level design tools to industry-leading verification technology
News from CoWare (4 June 2003)
Design verification with e
"Design verification with e", by Samir Palnitkar details a broad range of e-based topics including modelling, constraint-driven test generation, functional coverage and assertion checking
News from Verisity Design (4 June 2003)
Testbench supports more open standards
To better support system-level design flows, Verisity is supporting a wide variety of open standards through the Specman Elite testbench automation solution, including OVL, PSL/Sugar and SystemC
News from Verisity Design (4 June 2003)
Verification language set for standardisation
The IEEE Design Automation Standards Committee has approved a project to use the e verification language as a basis for standardisation
News from Verisity Design (4 June 2003)
Promotion for Sawicki
Joseph Sawicki has been promoted to Vice President and General Manager of the Mentor Graphics Design-to-Silicon Division
News from Mentor Graphics UK (4 June 2003)
Tools form basis of TSMC Reference Flow
User application article The Galaxy Design Platform and other Synopsys tools have been integrated into TSMC's advanced Reference Flow 4.0
News from Synopsys (4 June 2003)
Design platform takes on signal integrity tool
Galaxy SI is a new and complete signal integrity solution within the Galaxy Design Platform that addresses crosstalk delay, noise (glitch), IR (voltage) drop and electromigration
News from Synopsys (4 June 2003)
Toshiba signs off at 90nm with Star-RCXT
User application article Toshiba has standardised on Star-RCXT as the parasitic extraction tool for its 90nm TC300 design technology
News from Synopsys (4 June 2003)
Design planner qualified for Blue Logic
The Monterey design planner has been qualified for inclusion in IBM's Blue Logic standard ASIC design methodology
News from Monterey Design Systems (3 June 2003)
Set-top-box chips speed through to tape out
User application article STMicroelectronics has taped out two production 130nm SoC designs totalling 9 million gates, proving the value of Monterey Progressive Refinement technology for multi-million-gate nanometre chips
News from Monterey Design Systems (3 June 2003)
Software supports physics-based system simulation
Virginia Tech's Future Energy Electronics Centre has an innovative graduate curriculum based on Ansoft's electronic-design software for physics-based system simulation
News from Ansoft Europe (3 June 2003)
Free software takes easy approach to PCB design
The latest PCB123 software is designed specifically for those who need something quick and easy to get through the board design process
News from PCB123 (2 June 2003)
Hybrid power analyser speeds digital TV IC signoff
User application article LG has selected Acad's FinePower IR drop and electromigration analysis tool for the design and verification of a complex full chip used in its latest digital TV
News from Acad Corp (2 June 2003)
Platform licensing strategy proves popular
Wind River Systems has ended the first quarter of fiscal year 2004 with more than 1000 enterprise licence seats booked to date
News from Wind River Systems (2 June 2003)
Parallel characterisation speeds Spice
The Cadence Aptivia parallel characterisation option is reckoned to easily and cost-effectively slash circuit validation time up to 10x or more
News from Cadence Design Systems (2 June 2003)
Virtual silicon modelling made faster
VTOC 2 is the next-generation RTL to C/C++ virtual silicon modelling tool
News from Tenison EDA (2 June 2003)
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