Pair to link design tools with verification: News from CoWare

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CoWare and Verisity have agreed an integration roadmap for their products, which will connect new, breakthrough SystemC system-level design tools to industry-leading verification technology to form the foundation for a SystemC-based design ecosystem. The CoWare ConvergenSC product family is the EDA industry's first system-level design solution built expressly for SystemC. The product family will be integrated with Specman Elite, Verisity's flagship product for testbench automation.

With this integrated tool flow, users will be able to perform mixed-level block verification and system verification using ConvergenSC SystemC models and Verisity testbenches written in the e verification language.

"With ConvergenSC, designers can work at higher levels of abstraction, at the system level rather than the implementation level", said Mark Milligan, Vice President, Marketing, CoWare.

"They can mix implementation models with high-level system models, bringing faster simulation speed, ease of managing complexity, and the ability to refine system-level designs for implementation.

With the CoWare-Verisity flow, designers have access to the leading testbench technology to validate SystemC IP blocks for links to implementation".

"Tight integration of Specman Elite with ConvergenSC will provide SystemC users with more power and flexibility in their platform development and verification", said Francine Ferguson, Verisity's Vice President of Corporate and Strategic Marketing.

"In addition, SystemC users now have access to our broad range of e verification components (eVCs), such as our amba AHB eVC, which jumpstarts system-level verification".

By modelling in SystemC using ConvergenSC, designers can verify components and systems at several design abstraction levels.

They can build testbenches in the e verification language for Specman Elite or leverage previous investments in legacy IP testbenches for IP blocks modelled in SystemC.

System architects designing a new system will be able to develop a transactional prototype with ConvergenSC and use Verisity's cycle-accurate testbenches for the verification of high-speed transaction level models.

Users will be able to verify the full functionality of these high level models and shorten time to implementation.

The executable specification can be simulated and tested, and the design will be refined through abstraction levels as notions of timing and clocks are added.

The designer will be able to access the Verisity Specman Elite testbench in CoWare ConvergenSC for codesign and coverification.

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Pair to link design tools with verification

CoWare and Verisity have agreed an integration roadmap for their products, which will connect new, breakthrough SystemC system-level design tools to industry-leading verification technology.