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‘Vera’

An Electronicstalk guide

Start with the news release Graphical approach eases complex verification from Breker Verification Systems, which we summarised at the time by saying "Graph based functional test synthesis tool helps users to understand, define and analyse complicated verification requirements. ". Several months prior to that, we featured the news release Verification IP automates manual register checks from Denali Software: "IP automates functional verification of configuration registers for system-on-chip designs.".
 
In November 2006, we covered the news from Minicom Advanced Systems - take a look at Distribution system signs up for Wal-Mart which says: "The VDS player-to-screen multimedia distribution system has been installed as part of a digital signage network for 300 Wal-Mart de Mexico department stores.".
 
Take a look also at the news release from Jeda Technologies, Verification automation enters third generation, as well as Conference calls up design and verification papers from DVCon, and IEC award for testbench automation tool from Synopsys.
 

Latest stories...
Verification platform proves complex switch chips (October 2005)

StarGen has successfully verified two large, complex switching chips using VCS comprehensive RTL verification, Vera testbench automation and VCS Verification Library solutions.

Marvell goes from RTL to GDSII (October 2005)

Marvell has adopted Synopsys' Galaxy Design Platform as a RTL-to-GDSII design solution to develop networking and storage products.

Simulator made for networked design verification (August 2005)

Riviera-SNA addresses changing customer needs as ESL and ASIC manufacturers require an increased number of high-performance simulators online.

ASIC designer accelerates chip development (July 2005)

Silicon Logic Engineering is using the VCS comprehensive RTL verification solution and Vera testbench automation tool to accelerate its chip development process.

Collaboration aims for systems-level SoC design (June 2004)

Synopsys and Virtio are collaborating on a comprehensive electronic system level (ESL) solution that connects hardware and software development flows for leading SoC platforms.

Synopsys extends library support (June 2004)

Synopsys and ARM are collaborating to deliver Amba AXI verification intellectual property through Synopsys' DesignWare Library and DesignWare Verification Library.

Testbench technology aids RTL verification (May 2004)

The latest release of the VCS RTL verification solution extends its built-in testbench capabilities to include a rich set of advanced technologies.

Package accelerates verification regression (April 2004)

New enhancements to DesignPlayer will allow it to be seamlessly plugged into hardware regression environments, be driven by a variety of testbenches, and provide a 10x or greater performance gain.

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