Product category: Design and Development Software
News Release from: Zenasis Technologies | Subject: ZenTime
Edited by the Electronicstalk Editorial Team on 5 April 2005
Timing optimisation speeds
SoC to desktop market
Agilent Technologies has used the ZenTime cell-based timing optimisation tool to improve performance and accelerate time to silicon for a 90nm SoC for next-generation printer and imaging applications
Agilent Technologies has successfully used Zenasis' ZenTime cell-based timing optimisation tool to improve performance and accelerate time to silicon for a 90nm SoC design, intended for next-generation desktop printer and imaging applications. 'ZenTime is a unique EDA tool that helped us improve SoC performance to meet our design objectives', said Jay McDougal, IP Design Methodology Program Manager for Agilent's Imaging Solutions Division.
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'With ZenTime, we saw significant timing improvement on one of our most challenging IP cores'.
'Using ZenTime helps Agilent maintain its SoC integration and performance leadership'.
The Agilent SoC created with ZenTime operates at 400MHz, has 134 input/output signals and uses two million logic gates.
The SoC includes the ChipWrights CWv16 DSP core, a 2.5V PLL, DMA, amba AHB bus bridge, as well as bus monitor and arbiter.
With this SoC, Agilent extends its SoC leadership into the 90nm generation.
'It's gratifying to help companies like Agilent meet their design performance targets on time, and often ahead of schedule', said Jay Roy, CEO and cofounder of Zenasis Technologies.
'The combination of ZenTime and ZenCell Factory has been successfully used to improve benchmarked design performance by 10% or more after using today's best available optimisation tools and methodologies'.
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