Xilinx development kits aid FPGA design

Xilinx has announced six development kits as part of its Targeted Design Platforms for enabling developers to focus on innovation and differentiation when designing with FPGAs.

These development platforms for the Virtex-6 and Spartan-6 range significantly shorten the time it takes to reach optimal levels of system performance, while ensuring low levels of power consumption during system-on-chip (SoC) development.

The kits target embedded processing, DSP and the building of systems that require high-speed serial connectivity by providing design teams with optimised tool suites tuned to their design flow, fully functional IP and Targeted Reference Designs common to their areas of expertise.

The kits support development of designs with the Virtex-6 family of FPGAs for compute-intensive, high-speed, high-density SoC applications, or the Spartan-6 family of FPGAs.

Each kit includes low-power high-speed serial transceivers coupled with integrated PCI Express end-point blocks, integrated memory controllers and advanced high-performance digital-signal processing slices featuring pre-adder and advanced-control functionality.

Each kit is supported by an edition of the ISE Design Suite version 11.4, which delivers a 25 per cent runtime reduction for Spartan-6 FPGA designs and a 30 per cent runtime reduction for large, complex and highly utilised Virtex-6 SOC designs over the previous release.

All kits come with scalable development boards, fully functional domain-specific IP (intellectual property) cores, Targeted Reference Designs, complete documentation and cables for starting development out of the box.

The Targeted Reference Design at the heart of each kit is tuned to the design domain it supports and can be used 'as is' or modified and extended.

Customers are also provided with source code and simulation files that can be used within a design environment for building the end application.

The kits build upon the Spartan-6 FPGA and Virtex-6 FPGA base evaluation kits and will be followed by market-specific development kits offered by Xilinx and its ecosystem, such as the Virtex-6 FPGA Broadcast Connectivity Kit.

The Connectivity Development Kits contain Targeted Reference Designs that combine hard blocks within the FPGA with Xilinx connectivity IP and key third-party IP from Xilinx Alliance Program member Northwest Logic to implement a fully scalable PCIe to XAUI or GbEthernet Bridge.

Customers can choose fully compliant PCIe gen 1or gen 2 x1, x2 or x4 in the Virtex-6 FPGA kit, tune DMA settings to optimise system bandwidth, write and read data from external DDR3 memory, and link to a full XAUI interface within a system environment.

The Spartan-6 FPGA kit enables designers to link fully compliant PCIe gen 1 with GbEthernet using a full licence of Northwest Logic's DMA engine IP.

Both kits enable designers to measure system bandwidth and optimise settings for power and cost savings in a host-system environment.

The pre-loaded Targeted Reference Designs are optimised to demonstrate a fully functional connectivity system that uses four different clock domains running up to 250MHz.

The embedded development kits enable software developers to start development immediately using the Xilinx SDK environment that comes with the ISE Design Suite 11.4 Embedded Edition.

They can run and modify example code that is provided as part of the Targeted Reference Design, which utilises a fully implemented Microblaze 32-bit RISC soft processor core and a complete set of common processor peripherals including: UART, multi-port memory controller (MPMC), flash, tri-mode Ethernet MAC (TEMAC), general-purpose I/O (GPIO), I2C/SPI, timers/interrupt controllers and debug ports.

With a library of peripherals available as part of the EDK environment, hardware designers can use the Base System Builder feature to modify the reference design to achieve performance, power or resource optimisations.

The digital-signal processing development kits will enable algorithm and hardware developers to evaluate performance and implementation styles of common digital-signal processing elements that can be used as building blocks in an end application.

Each kit will contain a Targeted Reference Design optimised for Virtex-6 and Spartan-6 FPGAs and will utilise DSP IP and ISE Design Suite System Edition featuring the System Generator design environment.

Back to top