Virtex-6 FPGA family passes PCIe 2.0 compliance

Xilinx has announced that its latest-generation Virtex-6 family is compliant with the PCI Express (PCIe) 2.0 specification, delivering up to 50 per cent lower power than previous generations.

The second-generation PCIe block integrated in Xilinx Virtex-6 field-programmable gate arrays (FPGAs) has passed PCI-SIG PCIe 2.0 compliance and interoperability testing for one- to eight-lane configurations.

This milestone is expected to accelerate the mainstream development of high-bandwidth PCIe 2.0 systems for communications, multimedia, server and mobile platforms, enabling applications such as high-definition video, high-end medical imaging and industrial instrumentation.

In addition, Xilinx has once again teamed up with key alliance members Northwest Logic and PLDA to provide direct-memory-access (DMA) intellectual-property (IP) cores for Virtex-6 FPGAs.

This latest collaboration builds on the existing PCIe 2.0 soft IP for Virtex-5 FXT devices - the first FPGA to provide PCIe 2.0 x eight-lane support with the Northwest Logic DMA core.

DMA engines enable the efficient movement of data in systems, ensuring that the PCIe block in Virtex-6 FPGAs delivers maximum performance and bandwidth.

Designers can immediately begin the evaluation and design of PCIe 2.0-compliant systems in Virtex-6 FPGAs.

To assist in this effort, the Xilinx Core Generator system delivered in the ISE Design Suite provides the PCIe core, reference design and all the scripts, basic testbench and simulation models needed to streamline integration into customer designs.

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