FPGAs work with high-speed ADCs

FPGA reference design deserialises data streams from TI's ADS6000 ADC family.

Xilinx has released a Virtex-4 FPGA-based deserialiser reference design, application note and evaluation module jointly developed with Texas Instruments.

The new reference design, together with the accompanying application note, deserialises data streams from TI's ADS6000 analogue-to-digital convertor (ADC) family, providing designers a quick and easy solution with which to deploy products based on the latest advanced ADC device technology.

The evaluation module, available through TI (TSW1200EVM), consists of a circuit board and a set of preconfigured design files, which enable designers to prototype and evaluate the performance of the latest high-speed ADCs featuring serialised LVDS outputs.

Systems designers can now leverage the enormous serial-to-parallel processing capabilities and programmability of Xilinx Virtex-4 FPGAs to accelerate operations for specialised, high-performance functions.

The ability to achieve much higher levels of overall system performance is especially important for multi-channel systems in applications such as broadcast, medical, instrumentation and wireless infrastructure.

"The use of Xilinx Virtex-4 FPGA technology and its Iserdes feature, in combination with excellent support, allowed our design team to meet an extremely aggressive time to market window to provide a comprehensive evaluation module that will ultimately reduce cost and development time for our customers", said Heinz-Peter Beckemeyer, General Manager, High-Speed ADCs, Texas Instruments.

"Today's announcement represents yet another milestone in our ongoing collaboration with TI to successfully interface our FPGAs to their high-speed ADCs and DAC products", said David Gamba, Director of Vertical Market and Partnerships at Xilinx.

"By combining TI's leading ADC technology with the programmability and industry-leading high-speed serial performance of our Virtex-4 FPGAs, designers can leverage the evaluation module as a flexible and rapid prototyping environment for designing digital circuits that directly interface to the ADCs".

Built on the Virtex-4 LX25 platform, the Xilinx deserialiser reference design accepts up to four simultaneous ADC channels and provides automatic de- skew and clock alignment functions.

Each ADC output is serialised and transmitted through a separate LVDS serial pair.

An independent frame clock and serial data clock are provided to allow for easy deserialisation.

The Xilinx reference design exploits the unique Iserdes dedicated logic in the I/O of the Virtex-4 devices to provide the necessary timing to accept these extremely fast input signals and translate into parallel output buses, which can be more easily integrated.

The serial LVDS interface provides several distinct benefits to the system designer.

The lower pin count, both on the ADC and the FPGA, results in less routing lines, potentially fewer board layers, better immunity to external noise and extremely low crosstalk and injection of noise into the printed circuit board.

These advantages translate directly into lower system costs and improved system reliability when compared with legacy ADC communication interface technology.

The reference design (including VHDL code and test files) and application note are available free of charge from the Xilinx website.

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