FPGAs deliver feedback on power consumption

The System Monitor feature on Virtex-5 FPGAs provides thermal management and measurement of on-chip power supply voltages.

Xilinx has announced immediate availability of the System Monitor feature on all its Virtex-5 platform FPGAs.

Already onboard all Xilinx Virtex-5 devices, the solution provides customers with the industry's first analogue debug and system management tool for thermal management and measurement of on-chip power supply voltages.

Xilinx customers can access the full power of System Monitor by downloading the System Monitor wizard available with the latest ISE 9.1i IP Update I.

Designed by the Xilinx Dublin based IC design team, System Monitor is a sophisticated capability specifically created to address the challenges of increased on-chip power density that has accompanied increasing levels of FPGA integration and performance.

It facilitates easy access to key information during development and after deployment to help designers overcome these challenges to ensure performance and reliability.

"Our customers challenged our design team to integrate key monitoring features into the FPGA that require minimal development effort and provide enhanced visibility into the on-chip environment", said Anthony Collins, Staff Marketing Engineer, Mixed Signal, Advanced Products Group at Xilinx.

"The System Monitor capability available on all Virtex-5 devices has risen to the challenge by providing easy to access, on-chip power supply monitoring, temperature monitoring, and precision analogue inputs".

System Monitor is built around a fully specified 10bit 200Ksample/s general purpose analogue-to-digital convertor (ADC).

Automatic calibration and self check features ensure accurate and reliable measurements over a temperature range of -40 to +125C.

The ADC is used to digitise the outputs of on-chip analogue sensors and can also be used to monitor up to 17 external analogue inputs for the purpose of checking environmental aspects of the system performance.

The System Monitor feature is fully functional on power up and requires no design effort.

The complete solution is supported by Xilinx development software.

Additional benefits of the System Monitor capability include a programmable channel sequencer, measurement data averaging and the ability to set user defined alarm thresholds for on-chip sensors.

System Monitor can also be configured to initiate a chip level power down if necessary.

The capability will remain fully functional during power down, thus ensuring continuous monitoring, and can also initiate power-up under user-defined temperature conditions.

System Monitor is a feature available at no additional charge on all Virtex-5 FPGAs.

Tool support is provided to all ISE software users and beginning with ISE 9.1i IP Update I, an architectural wizard allows customers to easily integrate the capability.

Users of the ChipScope Pro tool can use the System Monitor capability during system debug.

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