Product category: Intellectual Property Cores
News Release from: True Circuits | Subject: PLL IP
Edited by the Electronicstalk Editorial Team on 18 November 2002
PLL IP aids digital TV SoC
The TeraLogic Group of Oak Technology is to use low-jitter PLL intellectual property from True Circuits in its Generation9 SoC, one of the industry's most advanced digital TV solutions
Related stories
Low-jitter hard macro wins key timing spot
Parama Networks has implemented a True Circuits clock generator PLL as the primary clocking macro in its new ADM-on-a-Chip, fabricated in UMC's 130nm process technology
Line of 65nm timing IP planned for 2007
True Circuits has announced a new line of silicon-proven TSMC 65nm phase-locked loop (PLL) and delay-locked loop (DLL) hard macros targeting high-speed timing applications
The TeraLogic Group of Oak Technology is to use low-jitter PLL intellectual property from True Circuits (TCI) in its Generation9 SoC, one of the industry's most advanced digital TV solutions. TCI's IP enabled Oak to incorporate multiple clock domains on a single SoC that previously required five separate ICs.
The Generation9 integrated circuit is a unique combination of features and functionality that will enable major consumer electronics manufacturers to substantially accelerate time-to-market and reduce the system cost of digital TV products.
Generation9 samples are now available and digital TV products based on the Generation9 architecture are expected to begin shipping in Q2 2003, establishing a new benchmark for lead-time from first silicon to production consumer electronics systems.
"True Circuit's low-jitter high-resolution clock generator PLL helped us produce a more flexible IC for our customers and enabled us to meet our time-to-market goals", said Gerard Yeh, Director of VLSI Design for Oak's TeraLogic Group.
Further reading
Soft modem chip integrates many PLLs
Multiple PLL hard macros have been used by fabless semiconductor company Icera in the Livanto ICE8020 wireless soft modem IC for 3G mobile phone and wireless devices
PLL hard macros save die space
A new line of phase-locked loop (PLL) hard macros from True Circuits occupy just one-third the die size of the company's current standard PLL products
"The True Circuits IP enabled us to set up multiple clock domains on a single IC that previously required five ICs - significantly cutting the cost associated with designing the digital circuits and allowing TV manufacturers to produce smaller units at lower cost".
True Circuits offers a large family of standardised PLL designs - deskew, clock generator, low bandwidth and spread-spectrum PLLs - that spans nearly all performance points and features typically requested by ASIC designers.
The designs are available for immediate delivery in a range of frequencies, multiplication factors and functions in CMOS processes from 0.25 to 0.13 micron and foundries such as TI, TSMC and UMC.
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